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Recent questions tagged interrupts
3
3 votes
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1 answer
184
184 views
GO Classes DPP | GATE CS | Operating System | Interrupts
Which of the following is/are true for interrupts?Interrupts temporarily suspend the currently running process to handle a specific event. When an interrupt occurs, the C...
GO Classes
184
views
asked
Jul 13
Operating System
goclasses
goclasses-cs-dpp
operating-system
goclasses-cs-dpp-day-321
goclasses-os-practice-questions
interrupts
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0
0 votes
0
0 answers
65
65 views
UGC NET CSE | December 2025 | Part 2 | Question: 82
Arrange the following events in correct order when an interrupt occurs during instruction execution.Save program counter (PC) and status register.Fetch interrupt vector f...
Shubham Sharma 2
65
views
asked
Apr 19
Others
ugcnetcse-dec2025
co-and-architecture
interrupts
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12
12 votes
3
3 answers
1.7k
1.7k views
GATE CSE 2026 | Set 2 | Question: 8
Consider the following two statements about interrupt handling mechanisms in a CPU.$\text{S1}$: In non-vectored interrupt mechanism, it usually takes more time to start t...
gatecse
1.7k
views
asked
Feb 23
CO & Architecture
gatecse-2026-set2
co-and-architecture
interrupts
one-mark
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1
1 vote
0
0 answers
19
19 views
I/O INTERRUPT QUESTION
Assume the number of clock cycles for a polling operation, including transferring to the polling routine, accessing the device, and restarting the user program, is 400 cy...
NIL DAS
19
views
asked
Dec 11, 2025
CO & Architecture
io-handling
interrupts
co-and-architecture
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0
0 votes
1
1 answer
362
362 views
UGC NET CSE | June 2025 | Part 2 | Question: 45
Consider the following interrupt protection levels in Linux, and arrange them in the increasing order of their priorities.User-Mode Programs (Preemptible)Bottom Half Inte...
Shubham Sharma 2
362
views
asked
Sep 10, 2025
Operating System
ugcnetcse-june2025
operating-system
interrupts
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2
2 votes
1
1 answer
306
306 views
UGC NET CSE | January 2025 | Part 2 | Question: 17
Which of the following is the correct sequence with regard to service routine?Save contents of processor registersTurn the interrupt facility onService the device whose f...
Shubham Sharma 2
306
views
asked
Sep 10, 2025
Operating System
ugcnetcse-jan2025
operating-system
interrupts
co-and-architecture
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0
0 votes
0
0 answers
176
176 views
UGC NET CSE | December 2023 | Part 2 | Question: 80
Arrange the following levels of interrupt protection within the Linux Kernel, in the order of increasing priority.user mode programsbottom half interrupt handlerskernel s...
Shubham Sharma 2
176
views
asked
Sep 9, 2025
Operating System
ugcnetcse-dec2023
operating-system
interrupts
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1
1 vote
1
1 answer
567
567 views
IO Organization : Comparing Programmed I/O and Interrupt I/O Performance
A device with data transfer rate 20 KB/sec is connected to a CPU. Data is transferred byte-wise. Let the interrupt overhead be 10 microseconds.What is the total time requ...
hrupam
567
views
asked
Apr 14, 2025
CO & Architecture
co-and-architecture
interrupts
io-handling
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15
15 votes
4
4 answers
6.8k
6.8k views
GATE CSE 2025 | Set 1 | Question: 1
Suppose a program is running on a non-pipelined single processor computer system. The computer is connected to an external device that can interrupt the processor asynchr...
Arjun
6.8k
views
asked
Feb 27, 2025
CO & Architecture
gatecse2025-set1
co-and-architecture
interrupts
easy
one-mark
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1
1 vote
0
0 answers
289
289 views
Disk Interrupt and timer interrupt
The answer is B and C , can someone please explain why disk interrupt and timer interrupt here are not the right answer
Athul 1
289
views
asked
Jan 8, 2025
Operating System
interrupts
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3
3 votes
1
1 answer
1.0k
1.0k views
DMA
Consider 4 MBPS IO devices connected to 64 bit CPU using DMA interface. 64 words data is transfer from the IO to memory using DMA interface. Main memory machine cycle tim...
Miracle124
1.0k
views
asked
Oct 18, 2024
CO & Architecture
co-and-architecture
dma
made-easy-test-series
interrupts
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3
3 votes
1
1 answer
884
884 views
ISRO CSE 2023 | Question: 5
In a vectored interruptThe branch address is assigned to a fixed location in memoryThe interrupting source supplies the branch information to the processorThe branch addr...
admin
884
views
asked
Sep 28, 2024
Digital Logic
isro-cse-2023
co-and-architecture
interrupts
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2
2 votes
2
2 answers
1.5k
1.5k views
ISRO CSE 2023 | Question: 32
Which of the following is false about interrupts?Interrupts can be triggered by a hardware or by a softwareHardware interrupts may be triggered by sending a signal to CPU...
admin
1.5k
views
asked
Sep 28, 2024
CO & Architecture
isro-cse-2023
co-and-architecture
interrupts
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2
2 votes
0
0 answers
427
427 views
Operating System - Trap and Interrupts
Which of the following statements is/are true regarding how the trap instruction (e.g., int n in x86) is invoked when a trap occurs in a system? When a user makes a syste...
mr.smooth
427
views
asked
Jun 12, 2024
Operating System
interrupts
operating-system
process-scheduling
trap
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2
2 votes
1
1 answer
1.4k
1.4k views
COA - DMA
A hard disk with a transfer rate of 1 Mbytes/ second is constantly transferring data to memory using DMA. The processor runs at 500 MHz, and takes 500 and 1000 clock cycl...
ajayraho
1.4k
views
asked
Nov 21, 2023
CO & Architecture
co-and-architecture
dma
interrupts
zeal-workbook
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0
0 votes
0
0 answers
427
427 views
UGC NET CSE | June 2023 | Part 2: 77
Given below are two statements: one is labelled as Assertion $\text{A}$ and the other is labelled as Reason $\text{R}$ .Assertion $\text{A}$ : I/O protection is ensured b...
admin
427
views
asked
Jul 28, 2023
Operating System
ugcnetcse-june2023-paper2
io-handling
hardware-trap
interrupts
assertion-reasoning
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48
48 votes
8
8 answers
20.8k
20.8k views
GATE CSE 2023 | Question: 24
A keyboard connected to a computer is used at a rate of $1$ keystroke per second. The computer system polls the keyboard every $10 \mathrm{~ms}$ (milli seconds) to check ...
admin
20.8k
views
asked
Feb 15, 2023
CO & Architecture
gatecse-2023
co-and-architecture
interrupts
numerical-answers
one-mark
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0
0 votes
0
0 answers
935
935 views
COA
Which of the following is/are true for a CPU which does not have any stack pointer registers?A Interrupts are not possible. B All subroutine calls and interrupts are po...
Overflow04
935
views
asked
Jan 24, 2023
CO & Architecture
co-and-architecture
self-doubt
interrupts
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3
3 votes
2
answers
2 answers
1.4k
1.4k views
I/O Modes | Process State Transition | COA & OS
MSQA ‘Running’ process is surely put into ‘Blocked/Wait’ state during while requesting for an I/O, in which of the following I/O modes?Synchronous I/OAsynchronous I/OInte...
Souvik33
1.4k
views
asked
Dec 2, 2022
CO & Architecture
operating-system
process-scheduling
co-and-architecture
dma
interrupts
input-output
multiple-selects
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0
0 votes
0
0 answers
432
432 views
UGC NET CSE | October 2022 | Part 1 | Question: 68
Consider the following two lists :$\begin{array}{ll} \text{List I} & \text{List II} \\ \\\text {(A) Stack overflow } & \text { (I) Software interrupt } \\\text {(B)} \mat...
admin
432
views
asked
Oct 23, 2022
Operating System
ugcnetcse-oct2022-paper1
operating-system
interrupts
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0
0 votes
1
1 answer
2.0k
2.0k views
Both internal and software interrupts are same ? Example : system call
Both internal and software caused by executing the program instructions . So both are same ?
its_vv
2.0k
views
asked
Jul 1, 2022
CO & Architecture
co-and-architecture
interrupts
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0
0 votes
1
1 answer
2.0k
2.0k views
NIELIT 2016 DEC Scientist B (CS) - Section B: 39
External Interrupt may not arise because ofillegal or erroneous use of an instruction.a timing device.external source.I/O devices.
admin
2.0k
views
asked
Mar 31, 2020
CO & Architecture
nielit2016dec-scientistb-cs
co-and-architecture
interrupts
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0
0 votes
2
2 answers
2.5k
2.5k views
NIELIT 2017 DEC Scientist B - Section B: 49
Which of the following is false?Interrupts which are initiated by an instruction are software interruptsWhen a subroutine is called, the address of the instruction follow...
admin
2.5k
views
asked
Mar 30, 2020
CO & Architecture
nielit2017dec-scientistb
co-and-architecture
interrupts
instruction-format
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