Recent questions tagged interrupts

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1

#Interrupts #OS Doubt.
When an interrupt occurs, an operating system can ignore the interrupt? Please tell the answer with reasoning? Thank you!

asked 4 days ago in Operating System by iarnav Loyal (8.6k points) | 23 views

–1 vote

0 answers

2

Gate questions
https://gateoverflow.in/1657/gate1998-1-20 https://gateoverflow.in/1300/gate2009-8-ugcnet-june2012-iii-58 The answer assumes execution means the execute phase in a pipelined system while in the other answer, execution means the execution of an entire instruction. How ... assume what? Option C is considered as wrong in the first link while it is the correct answer in the second link.

asked Sep 30 in CO & Architecture by gauravkc Loyal (6.4k points) | 12 views

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3

Vectored I/O

asked Sep 24 in CO & Architecture by Na462 Loyal (6.4k points) | 19 views

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4

Interrupt handling
Give an example each for a hardware interrupt, an explicit software interrupt, and an implicit software interrupt, and discuss the possible operations as part of the interrupt handler.

asked Sep 13 in Operating System by Debashish Deka Veteran (57.4k points) | 6 views

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1 answer

5

I/O operation
Please Explain Every Point :) Ans. All are Correct

asked Aug 13 in CO & Architecture by Na462 Loyal (6.4k points) | 57 views

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6

Interrupt
1)What is difference between internal interrupt and software interrupt? 2) What is difference between external interrupt and hardware interrupt?

asked Jul 26 in Operating System by srestha Veteran (98.3k points) | 26 views

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7

Interrupt Driven I/O
Consider a system employing interrupt driven I/O for a particular device that transfer data at an average of 8 KB/sec on a continuous basis. Consider interrupt processing takes about 100 μsec i.e. time to jump to ISR, execute it and return to main program. The ... /O device if interrupts occur for every byte is ________. [Assume 1 K = 1024] (Upto 2 decimal places) Ans. 0.81

asked Jul 25 in CO & Architecture by Na462 Loyal (6.4k points) | 56 views

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1 answer

8

UGCNET-July-2018-II-97
Match the items in List-I and List-II List - I List - II a Interrupts which can be delayed when a much highest priority interrupt has occurred i Normal b Unplanned interrupts which occur while executing a program ii Synchronous c Source of interrupt is in phase with the system clock iii Maskable iv Exception a-ii, b-i, c-iv a-ii, b-iv, c-iii a-iii, b-i, c-ii a-iii, b-iv, c-ii

asked Jul 13 in Others by Pooja Khatri Active (4.3k points) | 28 views

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0 answers

9

Vectored Interrupts
Are Vectored Interrupts possible in CPU having single Interrupt Request line? How/Why not?

asked Jun 2 in CO & Architecture by Harsh Kumar Junior (769 points) | 44 views

+1 vote

1 answer

10

I/O Interface
State whether the following statement is TRUE or FALSE and why ? In a microprocessor-based system, if a bus (DMA) request and an interrupt request arrive simultaneously, the microprocessor attends first to the bus request.

asked May 4 in CO & Architecture by ankitgupta.1729 Loyal (7.6k points) | 119 views

+7 votes

4 answers

11

GATE2018-9
The following are some events that occur after a device controller issues an interrupt while process $L$ is under execution. P. The processor pushes the process status of $L$ onto the control stack Q. The processor finishes the execution of the current ... based on the interrupt Which of the following is the correct order in which the events above occur? QPTRS PTRSQ TRPQS QTPRS

asked Feb 14 in Operating System by gatecse Boss (18.2k points) | 1.6k views

+2 votes

0 answers

12

Gateforum Tests
Can anybody explain in brief how to solve such numericals.

asked Jan 15 in CO & Architecture by vishal chugh Active (1.7k points) | 109 views

+1 vote

1 answer

13

Test Series

asked Jan 13 in CO & Architecture by vishal chugh Active (1.7k points) | 55 views

+3 votes

1 answer

14

Address after Halt instruction
Consider that the memory is byte addressable with size 16 bits, and the program has been loaded starting from memory location (2000)10. What will be the return address saved in the stack, if an interrupt occurs while the CPU has been halted after executing the HALT instruction? I am getting 2018.

asked Jan 2 in CO & Architecture by Shubhanshu Boss (15.5k points) | 263 views

+1 vote

1 answer

15

Interrupts
In case of Vectored interrupts,the I/o device send the vector address along with the I/o request or does it sends after it receives ack/INTA from CPU?

asked Dec 10, 2017 in Operating System by rahul sharma 5 Boss (25k points) | 70 views

0 votes

1 answer

16

Operating system:- Interrupts
when the interrupt occurs ,then a: process switching may be there b: context saving must be there c: both a and b d.None of these

asked Dec 8, 2017 in Operating System by rahul sharma 5 Boss (25k points) | 169 views

0 votes

1 answer

17

memory address saved on stack after interrupt

asked Dec 2, 2017 in CO & Architecture by Tuhin Dutta Loyal (8.2k points) | 236 views

+3 votes

1 answer

18

Interrupt
GATE -2009 A CPU generally handles an interrupt by executing an interrupt service routine As soon as an interrupt is raised. By checking the interrupt register at the end of fetch cycle. By checking the interrupt register after finishing the execution of the ... am having confusion between option A and C... For hardware interrupt option A is suitable and for software interrupt option C

asked Oct 26, 2017 in CO & Architecture by #Rahul (351 points) | 212 views

+3 votes

1 answer

19

Non vectored interrupt.
In non vectored interrupt, the address of ISR is a) assigned to fixed memory location b) obtained from interrupt vector table c) none of the above

asked Aug 28, 2017 in CO & Architecture by Xylene Active (3.9k points) | 412 views

0 votes

0 answers

20

NPTEL
Which of the following does not interrupt a running process? 1. A device 2. Timer 3. Power Failure 4. None of the above

asked Aug 23, 2017 in Operating System by gulsanchouhan (463 points) | 162 views

+1 vote

1 answer

21

Interrupt I/O|Made Easy test Series
The solution says that the answer should be 80, but applying the formula (x/y)*100, where x is 250 and y is 200 fraction comes out to be greater than 1. Am i making a mistake in interpreting x and y here?

asked Jul 8, 2017 in CO & Architecture by kimaya (61 points) | 210 views

+1 vote

1 answer

22

[COA] I/o Organization
Consider the following statements:- 1. Change program counter value 2. Change page table register context 3. Disable interrupt 4. Initiate I/o on a disk using memory mapped I/o which of the above can be executed in only in system mode? a.) 1,3,4 b)2,3,4 c.)1,2,3 d)2,4,1 Please give valid explanation with your answer.

asked May 27, 2017 in CO & Architecture by rahul sharma 5 Boss (25k points) | 165 views

0 votes

1 answer

23

[CO}Vectored interrupt
1. In case of vectored interrupt ,the i/o device will send vector address and then using this vector address,the IVT is referred which gives ISR address and then ISR is executed.So,the address that the I/o supplies is not the ISR ... fixed entries for ISR irrespective of vectored/non-vectored intrrupts? Is my understanding correct? Please correct me if i am missing anything?

asked May 18, 2017 in CO & Architecture by rahul sharma 5 Boss (25k points) | 252 views

+8 votes

2 answers

24

COA DMA doubt
What is formula for % of time CPU gets blocked?? Is it X(X+Y) or X/Y only??? What is formula for % of time CPU is consumed in Interuppt driven IO??? Formula for % of CPU slow down in interrupt driven IO???

asked Feb 6, 2017 in CO & Architecture by Rahul Jain25 Boss (11.6k points) | 2k views

+1 vote

3 answers

25

Interrupt I/O
Consider a system employing interrupt driven input/output for a particular device that transfers data at an average of 16 KB/s on a continuous basis. Assume that interrupt processing takes 50 μsec (i.e., the jump to the interrupt service routine (ISR), ... of processor time is consumed by this input/output device if it interrupt for every byte is _______ (Upto 3 decimal places).

asked Feb 2, 2017 in CO & Architecture by Pankaj Joshi Active (3k points) | 959 views

+2 votes

3 answers

26

INTERRUPTS AND SYSTEM CALLS
A CPU has 2 modes, privileged and non-privileged. In order to change the mode from previledged to non-previledged a) A hardware interrupt is needed b) A software interrupt is needed. c) A privileged instruction is needed. d) A non-privileged instruction is need.

asked Jan 4, 2017 in Operating System by sushmita Boss (14.6k points) | 160 views

+1 vote

0 answers

27

interrupt
Whenever a interrupt generates..mode changes(user to kernel mode)?

asked Dec 19, 2016 in CO & Architecture by vaishali jhalani Loyal (5.9k points) | 75 views

+10 votes

4 answers

28

GATE1990-4-ii
State whether the following statements are TRUE or FALSE with reason: The data transfer between memory and $I/O$ devices using programmed $I/O$ is faster than interrupt-driven $I/O$.

asked Nov 24, 2016 in CO & Architecture by makhdoom ghaya Boss (40.3k points) | 905 views

+1 vote

2 answers

29

GATE1987-2a
State whether the following statements are TRUE or FALSE In a microprocessor-based system, if a bus (DMA) request and an interrupt request arrive sumultaneously, the microprocessor attends first to the bus request.

asked Nov 9, 2016 in CO & Architecture by makhdoom ghaya Boss (40.3k points) | 314 views

+6 votes

1 answer

30

GATE1987-1-viii
On receiving an interrupt from a I/O device the CPU: Halts for a predetermined time. Hands over control of address bus and data bus to the interrupting device. Branches off to the interrupt service routine immediately. Branches off to the interrupt service routine after completion of the current instruction.

asked Nov 8, 2016 in CO & Architecture by makhdoom ghaya Boss (40.3k points) | 581 views

tags	tag:apple
author	user:martin
title	title:apple
content	content:apple
exclude	-tag:apple
force match	+apple
views	views:100
score	score:10
answers	answers:2
is accepted	isaccepted:true
is closed	isclosed:true

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