Recent questions tagged interrupts

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Andrew S. Tanenbaum (OS) Edition 4 Exercise 5 Question 37 (Page No. 432)
The clock interrupt handler on a certain computer requires $2\: msec$ (including process switching overhead) per clock tick. The clock runs at $60\: Hz.$ What fraction of the CPU is devoted to the clock?

asked Oct 28, 2019 in Operating System by Lakshman Patel RJIT Veteran (58.6k points) | 19 views

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Andrew S. Tanenbaum (OS) Edition 4 Exercise 5 Question 11 (Page No. 430)
A computer has a three-stage pipeline as shown in Fig. 1-7(a). On each clock cycle, one new instruction is fetched from memory at the address pointed to by the PC and put into the pipeline and ... instruction of the interrupt handler is fetched into the pipeline. Does this machine have precise interrupts? Defend your answer.

asked Oct 28, 2019 in Operating System by Lakshman Patel RJIT Veteran (58.6k points) | 30 views

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Andrew S. Tanenbaum (OS) Edition 4 Exercise 5 Question 10 (Page No. 430)
In Fig. 5-9(b), the interrupt is not acknowledged until after the next character has been output to the printer. Could it have equally well been acknowledged right at the start of the interrupt service procedure? If so, give one reason for doing it at the end, as in the text. If not, why not?

asked Oct 28, 2019 in Operating System by Lakshman Patel RJIT Veteran (58.6k points) | 9 views

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Andrew S. Tanenbaum (OS) Edition 4 Exercise 5 Question 9 (Page No. 430)
CPU architects know that operating system writers hate imprecise interrupts. One way to please the OS folks is for the CPU to stop issuing new instructions when an interrupt is signaled, but allow all the ... executed to finish, then force the interrupt. Does this approach have any disadvantages? Explain your answer.

asked Oct 28, 2019 in Operating System by Lakshman Patel RJIT Veteran (58.6k points) | 6 views

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Andrew S. Tanenbaum (OS) Edition 4 Exercise 5 Question 8 (Page No. 430)
Suppose that a computer can read or write a memory word in $5 nsec.$ Also suppose that when an interrupt occurs, all $32$ CPU registers, plus the program counter and PSW are pushed onto the stack. What is the maximum number of interrupts per second this machine can process?

asked Oct 28, 2019 in Operating System by Lakshman Patel RJIT Veteran (58.6k points) | 4 views

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Andrew S. Tanenbaum (OS) Edition 4 Exercise 5 Question 4 (Page No. 429)
Explain the tradeoffs between precise and imprecise interrupts on a superscalar machine.

asked Oct 28, 2019 in Operating System by Lakshman Patel RJIT Veteran (58.6k points) | 4 views

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Andrew S. Tanenbaum (OS) Edition 4 Exercise 2 Question 31 (Page No. 176)
How could an operating system that can disable interrupts implement semaphores?

asked Oct 25, 2019 in Operating System by Lakshman Patel RJIT Veteran (58.6k points) | 13 views

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Andrew S. Tanenbaum (OS) Edition 4 Exercise 2 Question 22 (Page No. 175)
Suppose that an operating system does not have anything like the select system call to see in advance if it is safe to read from a file, pipe, or device, but it does allow alarm clocks to be set that interrupt blocked system calls. Is it possible to implement a threads package in user space under these conditions? Discuss.

asked Oct 25, 2019 in Operating System by Lakshman Patel RJIT Veteran (58.6k points) | 4 views

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Andrew S. Tanenbaum (OS) Edition 4 Exercise 2 Question 21 (Page No. 175)
Consider a system in which threads are implemented entirely in user space, with the run-time system getting a clock interrupt once a second. Suppose that a clock interrupt occurs while some thread is executing in the run-time system. What problem might occur? Can you suggest a way to solve it?

asked Oct 25, 2019 in Operating System by Lakshman Patel RJIT Veteran (58.6k points) | 9 views

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Andrew S. Tanenbaum (OS) Edition 4 Exercise 2 Question 16 (Page No. 175)
Can a thread ever be preempted by a clock interrupt? If so, under what circumstances? If not, why not?

asked Oct 24, 2019 in Operating System by Lakshman Patel RJIT Veteran (58.6k points) | 9 views

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Andrew S. Tanenbaum (OS) Edition 4 Exercise 2 Question 15 (Page No. 175)
Why would a thread ever voluntarily give up the CPU by calling thread yield? After all, since there is no periodic clock interrupt, it may never get the CPU back.

asked Oct 24, 2019 in Operating System by Lakshman Patel RJIT Veteran (58.6k points) | 9 views

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Andrew S. Tanenbaum (OS) Edition 4 Exercise 2 Question 3 (Page No. 174)
On all current computers, at least part of the interrupt handlers are written in assembly language. Why?

asked Oct 24, 2019 in Operating System by Lakshman Patel RJIT Veteran (58.6k points) | 6 views

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Andrew S. Tanenbaum (OS) Edition 4 Exercise 2 Question 2 (Page No. 174)
Suppose that you were to design an advanced computer architecture that did process switching in hardware, instead of having interrupts. What information would the CPU need? Describe how the hardware process switching might work.

asked Oct 24, 2019 in Operating System by Lakshman Patel RJIT Veteran (58.6k points) | 7 views

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Andrew S. Tanenbaum (OS) Edition 4 Exercise 1 Question 16 (Page No. 82)
When a user program makes a system call to read or write a disk file, it provides an indication of which file it wants, a pointer to the data buffer, and the count. Control is then transferred to the operating ... What about the case of writing to the disk? Need the caller be blocked awaiting completion of the disk transfer?

asked Oct 23, 2019 in Operating System by Lakshman Patel RJIT Veteran (58.6k points) | 2 views

+1 vote

1 answer

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Interrupt Service Routing ( Applied course Mock 3)
Consider a process P1 that is executing on a Linux-like OS on a single core system. When P1 is executing, a disk interrupt occurs, causing P1 to go to kernel mode to service that interrupt. The interrupt delivers all the disk blocks that unblock ... is ready P1 is ready and P2 is running P1 is running and P2 is ready P1 is blocked and P2 is ready

asked Jan 15, 2019 in Operating System by Mk Utkarsh Boss (36.4k points) | 144 views

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16

DMA,interrupts
True/false 1. To access bus the DMA does not issue an interrupt it is done through DMA-request and DMA-acknowledge wires. Interrupt is issued by DMA to CPU only after complete data is transferred to the specific memory address by DMA. 2. DMA interrupts the CPU whenever it needs to initiate I/O and also when it has finished I/O transfers.

asked Jan 4, 2019 in CO and Architecture by Gurdeep Saini Boss (10.6k points) | 162 views

+1 vote

1 answer

17

I/O-COA
I think percentage of processor time consumed should be $\frac{ \,ISR\,time}{ISR\,time+\,Data\,Transfer\,Time}=\frac{100}{100+122}$. Is it correct?

asked Oct 30, 2018 in CO and Architecture by Ayush Upadhyaya Boss (29k points) | 197 views

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Vectored or non vectored Interrupt
In this state diagram of interrupt, where interrupt service routine is used? Why both hardware and software control are needed to service an interrupt? PC,PSW and ISR how it execute one after another, I just getting problem which is the order of coming these to process interrupt and why?(Any easy discussion on this)

asked Oct 27, 2018 in Operating System by srestha Veteran (118k points) | 520 views

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19

Non Vectored Interrupt

asked Oct 21, 2018 in CO and Architecture by Na462 Loyal (7k points) | 207 views

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20

#Interrupts #OS Doubt.
When an interrupt occurs, an operating system can ignore the interrupt? Please tell the answer with reasoning? Thank you!

asked Oct 12, 2018 in Operating System by iarnav Loyal (8.4k points) | 67 views

–1 vote

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21

Gate questions
https://gateoverflow.in/1657/gate1998-1-20 https://gateoverflow.in/1300/gate2009-8-ugcnet-june2012-iii-58 The answer assumes execution means the execute phase in a pipelined system while in the other answer, execution means the execution of an entire instruction. How ... assume what? Option C is considered as wrong in the first link while it is the correct answer in the second link.

asked Sep 30, 2018 in CO and Architecture by gauravkc Loyal (7.8k points) | 101 views

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22

Vectored I/O

asked Sep 24, 2018 in CO and Architecture by Na462 Loyal (7k points) | 118 views

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23

Interrupt handling
Give an example each for a hardware interrupt, an explicit software interrupt, and an implicit software interrupt, and discuss the possible operations as part of the interrupt handler.

asked Sep 13, 2018 in Operating System by dd Veteran (57.2k points) | 42 views

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I/O operation
Please Explain Every Point :) Ans. All are Correct

asked Aug 13, 2018 in CO and Architecture by Na462 Loyal (7k points) | 406 views

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25

Interrupt
1)What is difference between internal interrupt and software interrupt? 2) What is difference between external interrupt and hardware interrupt?

asked Jul 26, 2018 in Operating System by srestha Veteran (118k points) | 89 views

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2 answers

26

MadeEasy Test Series: CO & Architecture - Io Handling
Consider a system employing interrupt driven I/O for a particular device that transfer data at an average of 8 KB/sec on a continuous basis. Consider interrupt processing takes about 100 μsec i.e. time to jump to ISR, execute it and return ... if interrupts occur for every byte is ________. [Assume 1 K = 1024] (Upto 2 decimal places) Ans. 0.81

asked Jul 25, 2018 in CO and Architecture by Na462 Loyal (7k points) | 422 views

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2 answers

27

UGCNET-July-2018-II-97
Match the items in List-I and List-II List - I List - II a Interrupts which can be delayed when a much highest priority interrupt has occurred i Normal b Unplanned interrupts which occur while executing a program ii Synchronous c Source of interrupt is in phase with the system clock iii Maskable iv Exception a-ii, b-i, c-iv a-ii, b-iv, c-iii a-iii, b-i, c-ii a-iii, b-iv, c-ii

asked Jul 13, 2018 in Others by Pooja Khatri Boss (10.9k points) | 338 views

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28

Vectored Interrupts
Are Vectored Interrupts possible in CPU having single Interrupt Request line? How/Why not?

asked Jun 2, 2018 in CO and Architecture by Harsh Kumar Active (1.3k points) | 127 views

+1 vote

1 answer

29

I/O Interface
State whether the following statement is TRUE or FALSE and why ? In a microprocessor-based system, if a bus (DMA) request and an interrupt request arrive simultaneously, the microprocessor attends first to the bus request.

asked May 4, 2018 in CO and Architecture by ankitgupta.1729 Boss (17k points) | 327 views

+14 votes

4 answers

30

GATE2018-9
The following are some events that occur after a device controller issues an interrupt while process $L$ is under execution. P. The processor pushes the process status of $L$ onto the control stack Q. The processor finishes the execution of the current ... value based on the interrupt Which of the following is the correct order in which the events above occur? QPTRS PTRSQ TRPQS QTPRS

asked Feb 14, 2018 in Operating System by gatecse Boss (17.5k points) | 2.9k views

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