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Recent questions tagged interrupts

0 votes
1 answer
1
NIELIT 2016 DEC Scientist B (CS) - Section B: 39
External Interrupt may not arise because of illegal or erroneous use of an instruction. a timing device. external source. I/O devices.
External Interrupt may not arise because of illegal or erroneous use of an instruction. a timing device. external source. I/O devices.
asked Mar 31, 2020 in CO and Architecture Lakshman Patel RJIT 582 views
0 votes
1 answer
2
NIELIT 2017 DEC Scientist B - Section B: 49
Which of the following is false? Interrupts which are initiated by an instruction are software interrupts When a subroutine is called, the address of the instruction following the CALL instruction is stored in the stack pointer A micro program which is written as $0$’s and $1$’s is a binary micro program None of the options
Which of the following is false? Interrupts which are initiated by an instruction are software interrupts When a subroutine is called, the address of the instruction following the CALL instruction is stored in the stack pointer A micro program which is written as $0$’s and $1$’s is a binary micro program None of the options
asked Mar 30, 2020 in CO and Architecture Lakshman Patel RJIT 568 views
0 votes
1 answer
3
UGCNET-Jan2017-III: 1
Which of the following is an interrupt according to temporal relationship with system clock? Maskable interrupt Periodic interrupt Division by zero Synchronous interrupt
Which of the following is an interrupt according to temporal relationship with system clock? Maskable interrupt Periodic interrupt Division by zero Synchronous interrupt
asked Mar 24, 2020 in CO and Architecture jothee 264 views
7 votes
1 answer
4
GATE CSE 2020 | Question: 3
Consider the following statements. Daisy chaining is used to assign priorities in attending interrupts. When a device raises a vectored interrupt, the CPU does polling to identify the source of interrupt. In polling, the CPU periodically checks the status bits to know if any ... . Which of the above statements is/are TRUE? Ⅰ and Ⅱ only Ⅰ and Ⅳ only Ⅰ and Ⅲ only Ⅲ only
Consider the following statements. Daisy chaining is used to assign priorities in attending interrupts. When a device raises a vectored interrupt, the CPU does polling to identify the source of interrupt. In polling, the CPU periodically checks the status bits to know if any device needs its ... same time. Which of the above statements is/are TRUE? Ⅰ and Ⅱ only Ⅰ and Ⅳ only Ⅰ and Ⅲ only Ⅲ only
asked Feb 12, 2020 in CO and Architecture Arjun 4.1k views
1 vote
1 answer
5
Andrew S. Tanenbaum (OS) Edition 4 Exercise 5 Question 37 (Page No. 432)
The clock interrupt handler on a certain computer requires $2\: msec$ (including process switching overhead) per clock tick. The clock runs at $60\: Hz.$ What fraction of the CPU is devoted to the clock?
The clock interrupt handler on a certain computer requires $2\: msec$ (including process switching overhead) per clock tick. The clock runs at $60\: Hz.$ What fraction of the CPU is devoted to the clock?
asked Oct 28, 2019 in Operating System Lakshman Patel RJIT 500 views
0 votes
0 answers
6
Andrew S. Tanenbaum (OS) Edition 4 Exercise 5 Question 11 (Page No. 430)
A computer has a three-stage pipeline as shown in Fig. 1-7(a). On each clock cycle, one new instruction is fetched from memory at the address pointed to by the PC and put into the pipeline and ... instruction of the interrupt handler is fetched into the pipeline. Does this machine have precise interrupts? Defend your answer.
A computer has a three-stage pipeline as shown in Fig. 1-7(a). On each clock cycle, one new instruction is fetched from memory at the address pointed to by the PC and put into the pipeline and the PC advanced. Each instruction occupies exactly ... stage and the first instruction of the interrupt handler is fetched into the pipeline. Does this machine have precise interrupts? Defend your answer.
asked Oct 28, 2019 in CO and Architecture Lakshman Patel RJIT 354 views
1 vote
0 answers
7
Andrew S. Tanenbaum (OS) Edition 4 Exercise 5 Question 10 (Page No. 430)
In Fig. 5-9(b), the interrupt is not acknowledged until after the next character has been output to the printer. Could it have equally well been acknowledged right at the start of the interrupt service procedure? If so, give one reason for doing it at the end, as in the text. If not, why not?
In Fig. 5-9(b), the interrupt is not acknowledged until after the next character has been output to the printer. Could it have equally well been acknowledged right at the start of the interrupt service procedure? If so, give one reason for doing it at the end, as in the text. If not, why not?
asked Oct 28, 2019 in Operating System Lakshman Patel RJIT 120 views
0 votes
0 answers
8
Andrew S. Tanenbaum (OS) Edition 4 Exercise 5 Question 9 (Page No. 430)
CPU architects know that operating system writers hate imprecise interrupts. One way to please the OS folks is for the CPU to stop issuing new instructions when an interrupt is signaled, but allow all the ... executed to finish, then force the interrupt. Does this approach have any disadvantages? Explain your answer.
CPU architects know that operating system writers hate imprecise interrupts. One way to please the OS folks is for the CPU to stop issuing new instructions when an interrupt is signaled, but allow all the instructions currently being executed to finish, then force the interrupt. Does this approach have any disadvantages? Explain your answer.
asked Oct 28, 2019 in Operating System Lakshman Patel RJIT 82 views
1 vote
0 answers
9
Andrew S. Tanenbaum (OS) Edition 4 Exercise 5 Question 8 (Page No. 430)
Suppose that a computer can read or write a memory word in $5 nsec.$ Also suppose that when an interrupt occurs, all $32$ CPU registers, plus the program counter and PSW are pushed onto the stack. What is the maximum number of interrupts per second this machine can process?
Suppose that a computer can read or write a memory word in $5 nsec.$ Also suppose that when an interrupt occurs, all $32$ CPU registers, plus the program counter and PSW are pushed onto the stack. What is the maximum number of interrupts per second this machine can process?
asked Oct 28, 2019 in Operating System Lakshman Patel RJIT 73 views
0 votes
0 answers
12
Andrew S. Tanenbaum (OS) Edition 4 Exercise 2 Question 22 (Page No. 175)
Suppose that an operating system does not have anything like the select system call to see in advance if it is safe to read from a file, pipe, or device, but it does allow alarm clocks to be set that interrupt blocked system calls. Is it possible to implement a threads package in user space under these conditions? Discuss.
Suppose that an operating system does not have anything like the select system call to see in advance if it is safe to read from a file, pipe, or device, but it does allow alarm clocks to be set that interrupt blocked system calls. Is it possible to implement a threads package in user space under these conditions? Discuss.
asked Oct 25, 2019 in Operating System Lakshman Patel RJIT 139 views
0 votes
1 answer
13
Andrew S. Tanenbaum (OS) Edition 4 Exercise 2 Question 21 (Page No. 175)
Consider a system in which threads are implemented entirely in user space, with the run-time system getting a clock interrupt once a second. Suppose that a clock interrupt occurs while some thread is executing in the run-time system. What problem might occur? Can you suggest a way to solve it?
Consider a system in which threads are implemented entirely in user space, with the run-time system getting a clock interrupt once a second. Suppose that a clock interrupt occurs while some thread is executing in the run-time system. What problem might occur? Can you suggest a way to solve it?
asked Oct 25, 2019 in Operating System Lakshman Patel RJIT 265 views
0 votes
1 answer
15
Andrew S. Tanenbaum (OS) Edition 4 Exercise 2 Question 15 (Page No. 175)
Why would a thread ever voluntarily give up the CPU by calling thread yield? After all, since there is no periodic clock interrupt, it may never get the CPU back.
Why would a thread ever voluntarily give up the CPU by calling thread yield? After all, since there is no periodic clock interrupt, it may never get the CPU back.
asked Oct 24, 2019 in Operating System Lakshman Patel RJIT 332 views
0 votes
1 answer
17
Andrew S. Tanenbaum (OS) Edition 4 Exercise 2 Question 2 (Page No. 174)
Suppose that you were to design an advanced computer architecture that did process switching in hardware, instead of having interrupts. What information would the CPU need? Describe how the hardware process switching might work.
Suppose that you were to design an advanced computer architecture that did process switching in hardware, instead of having interrupts. What information would the CPU need? Describe how the hardware process switching might work.
asked Oct 24, 2019 in Operating System Lakshman Patel RJIT 87 views
0 votes
0 answers
18
Andrew S. Tanenbaum (OS) Edition 4 Exercise 1 Question 16 (Page No. 82)
When a user program makes a system call to read or write a disk file, it provides an indication of which file it wants, a pointer to the data buffer, and the count. Control is then transferred to the operating ... What about the case of writing to the disk? Need the caller be blocked awaiting completion of the disk transfer?
When a user program makes a system call to read or write a disk file, it provides an indication of which file it wants, a pointer to the data buffer, and the count. Control is then transferred to the operating system, which calls the appropriate driver. Suppose that ... no data for it). What about the case of writing to the disk? Need the caller be blocked awaiting completion of the disk transfer?
asked Oct 23, 2019 in Operating System Lakshman Patel RJIT 68 views
2 votes
1 answer
19
Interrupt Service Routing ( Applied course Mock 3)
Consider a process P1 that is executing on a Linux-like OS on a single core system. When P1 is executing, a disk interrupt occurs, causing P1 to go to kernel mode to service that interrupt. The interrupt delivers all the disk blocks that unblock ... is ready P1 is ready and P2 is running P1 is running and P2 is ready P1 is blocked and P2 is ready
Consider a process P1 that is executing on a Linux-like OS on a single core system. When P1 is executing, a disk interrupt occurs, causing P1 to go to kernel mode to service that interrupt. The interrupt delivers all the disk blocks that unblock a process P2 (which blocked earlier ... is ready and P2 is ready P1 is ready and P2 is running P1 is running and P2 is ready P1 is blocked and P2 is ready
asked Jan 15, 2019 in Operating System Mk Utkarsh 565 views
1 vote
2 answers
20
DMA,interrupts
True/false 1. To access bus the DMA does not issue an interrupt it is done through DMA-request and DMA-acknowledge wires. Interrupt is issued by DMA to CPU only after complete data is transferred to the specific memory address by DMA. 2. DMA interrupts the CPU whenever it needs to initiate I/O and also when it has finished I/O transfers.
True/false 1. To access bus the DMA does not issue an interrupt it is done through DMA-request and DMA-acknowledge wires. Interrupt is issued by DMA to CPU only after complete data is transferred to the specific memory address by DMA. 2. DMA interrupts the CPU whenever it needs to initiate I/O and also when it has finished I/O transfers.
asked Jan 4, 2019 in CO and Architecture Gurdeep Saini 466 views
1 vote
1 answer
21
I/O-COA
I think percentage of processor time consumed should be $\frac{ \,ISR\,time}{ISR\,time+\,Data\,Transfer\,Time}=\frac{100}{100+122}$. Is it correct?
I think percentage of processor time consumed should be $\frac{ \,ISR\,time}{ISR\,time+\,Data\,Transfer\,Time}=\frac{100}{100+122}$. Is it correct?
asked Oct 30, 2018 in CO and Architecture Ayush Upadhyaya 613 views
1 vote
0 answers
22
Vectored or non vectored Interrupt
In this state diagram of interrupt, where interrupt service routine is used? Why both hardware and software control are needed to service an interrupt? PC,PSW and ISR how it execute one after another, I just getting problem which is the order of coming these to process interrupt and why?(Any easy discussion on this)
In this state diagram of interrupt, where interrupt service routine is used? Why both hardware and software control are needed to service an interrupt? PC,PSW and ISR how it execute one after another, I just getting problem which is the order of coming these to process interrupt and why?(Any easy discussion on this)
asked Oct 27, 2018 in Operating System srestha 1.3k views
0 votes
2 answers
23
Non Vectored Interrupt
asked Oct 21, 2018 in CO and Architecture Na462 617 views
0 votes
1 answer
24
#Interrupts #OS Doubt.
When an interrupt occurs, an operating system can ignore the interrupt? Please tell the answer with reasoning? Thank you!
When an interrupt occurs, an operating system can ignore the interrupt? Please tell the answer with reasoning? Thank you!
asked Oct 12, 2018 in Operating System iarnav 140 views
0 votes
0 answers
25
Gate questions
https://gateoverflow.in/1657/gate1998-1-20 https://gateoverflow.in/1300/gate2009-8-ugcnet-june2012-iii-58 The answer assumes execution means the execute phase in a pipelined system while in the other answer, execution means the execution of an entire instruction. How ... assume what? Option C is considered as wrong in the first link while it is the correct answer in the second link.
https://gateoverflow.in/1657/gate1998-1-20 https://gateoverflow.in/1300/gate2009-8-ugcnet-june2012-iii-58 The answer assumes execution means the execute phase in a pipelined system while in the other answer, execution means the execution of an entire instruction. How to know when to assume what? Option C is considered as wrong in the first link while it is the correct answer in the second link.
asked Sep 30, 2018 in CO and Architecture gauravkc 194 views
1 vote
1 answer
26
Vectored I/O
asked Sep 24, 2018 in CO and Architecture Na462 297 views
0 votes
0 answers
27
Interrupt handling
Give an example each for a hardware interrupt, an explicit software interrupt, and an implicit software interrupt, and discuss the possible operations as part of the interrupt handler.
Give an example each for a hardware interrupt, an explicit software interrupt, and an implicit software interrupt, and discuss the possible operations as part of the interrupt handler.
asked Sep 13, 2018 in Operating System dd 153 views
3 votes
1 answer
28
I/O operation
Please Explain Every Point :) Ans. All are Correct
Please Explain Every Point :) Ans. All are Correct
asked Aug 13, 2018 in CO and Architecture Na462 952 views
0 votes
0 answers
29
Interrupt
1)What is difference between internal interrupt and software interrupt? 2) What is difference between external interrupt and hardware interrupt?
1)What is difference between internal interrupt and software interrupt? 2) What is difference between external interrupt and hardware interrupt?
asked Jul 26, 2018 in Operating System srestha 354 views
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