Recent questions tagged interrupts

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1

GATEBOOK-2019 Mock Test1-16
Which of the following can make a processor transition from user mode to kernel mode? A user process executing trap instruction A user process causing an exception Receiving an interrupt All of the above

asked Jan 19 in CO and Architecture by GATEBOOK Boss (11.4k points) | 95 views

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2

Interrupt Service Routing ( Applied course Mock 3)
Consider a process P1 that is executing on a Linux-like OS on a single core system. When P1 is executing, a disk interrupt occurs, causing P1 to go to kernel mode to service that interrupt. The interrupt delivers all the disk blocks that unblock ... is ready P1 is ready and P2 is running P1 is running and P2 is ready P1 is blocked and P2 is ready

asked Jan 15 in Operating System by Mk Utkarsh Boss (34.8k points) | 109 views

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1 answer

3

DMA,interrupts
True/false 1. To access bus the DMA does not issue an interrupt it is done through DMA-request and DMA-acknowledge wires. Interrupt is issued by DMA to CPU only after complete data is transferred to the specific memory address by DMA. 2. DMA interrupts the CPU whenever it needs to initiate I/O and also when it has finished I/O transfers.

asked Jan 4 in CO and Architecture by Gurdeep Saini Loyal (9.9k points) | 90 views

+1 vote

1 answer

4

I/O-COA
I think percentage of processor time consumed should be $\frac{ \,ISR\,time}{ISR\,time+\,Data\,Transfer\,Time}=\frac{100}{100+122}$. Is it correct?

asked Oct 30, 2018 in CO and Architecture by Ayush Upadhyaya Boss (25.5k points) | 118 views

+1 vote

0 answers

5

Vectored or non vectored Interrupt
In this state diagram of interrupt, where interrupt service routine is used? Why both hardware and software control are needed to service an interrupt? PC,PSW and ISR how it execute one after another, I just getting problem which is the order of coming these to process interrupt and why?(Any easy discussion on this)

asked Oct 27, 2018 in Operating System by srestha Veteran (113k points) | 409 views

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2 answers

6

Non Vectored Interrupt

asked Oct 21, 2018 in CO and Architecture by Na462 Loyal (6.7k points) | 150 views

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1 answer

7

#Interrupts #OS Doubt.
When an interrupt occurs, an operating system can ignore the interrupt? Please tell the answer with reasoning? Thank you!

asked Oct 12, 2018 in Operating System by iarnav Loyal (8k points) | 60 views

–1 vote

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8

Gate questions
https://gateoverflow.in/1657/gate1998-1-20 https://gateoverflow.in/1300/gate2009-8-ugcnet-june2012-iii-58 The answer assumes execution means the execute phase in a pipelined system while in the other answer, execution means the execution of an entire instruction. How ... assume what? Option C is considered as wrong in the first link while it is the correct answer in the second link.

asked Sep 30, 2018 in CO and Architecture by gauravkc Loyal (7.8k points) | 80 views

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9

Vectored I/O

asked Sep 24, 2018 in CO and Architecture by Na462 Loyal (6.7k points) | 86 views

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10

Interrupt handling
Give an example each for a hardware interrupt, an explicit software interrupt, and an implicit software interrupt, and discuss the possible operations as part of the interrupt handler.

asked Sep 13, 2018 in Operating System by dd Veteran (56.6k points) | 27 views

+2 votes

1 answer

11

I/O operation
Please Explain Every Point :) Ans. All are Correct

asked Aug 13, 2018 in CO and Architecture by Na462 Loyal (6.7k points) | 304 views

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12

Interrupt
1)What is difference between internal interrupt and software interrupt? 2) What is difference between external interrupt and hardware interrupt?

asked Jul 26, 2018 in Operating System by srestha Veteran (113k points) | 74 views

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1 answer

13

MadeEasy Test Series: CO & Architecture - Io Handling
Consider a system employing interrupt driven I/O for a particular device that transfer data at an average of 8 KB/sec on a continuous basis. Consider interrupt processing takes about 100 μsec i.e. time to jump to ISR, execute it and return ... if interrupts occur for every byte is ________. [Assume 1 K = 1024] (Upto 2 decimal places) Ans. 0.81

asked Jul 25, 2018 in CO and Architecture by Na462 Loyal (6.7k points) | 262 views

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2 answers

14

UGCNET-July-2018-II-97
Match the items in List-I and List-II List - I List - II a Interrupts which can be delayed when a much highest priority interrupt has occurred i Normal b Unplanned interrupts which occur while executing a program ii Synchronous c Source of interrupt is in phase with the system clock iii Maskable iv Exception a-ii, b-i, c-iv a-ii, b-iv, c-iii a-iii, b-i, c-ii a-iii, b-iv, c-ii

asked Jul 13, 2018 in Others by Pooja Khatri Boss (10.8k points) | 281 views

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15

Vectored Interrupts
Are Vectored Interrupts possible in CPU having single Interrupt Request line? How/Why not?

asked Jun 2, 2018 in CO and Architecture by Harsh Kumar Active (1.2k points) | 108 views

+1 vote

1 answer

16

I/O Interface
State whether the following statement is TRUE or FALSE and why ? In a microprocessor-based system, if a bus (DMA) request and an interrupt request arrive simultaneously, the microprocessor attends first to the bus request.

asked May 4, 2018 in CO and Architecture by ankitgupta.1729 Boss (14k points) | 250 views

+12 votes

4 answers

17

GATE2018-9
The following are some events that occur after a device controller issues an interrupt while process $L$ is under execution. P. The processor pushes the process status of $L$ onto the control stack Q. The processor finishes the execution of the current ... value based on the interrupt Which of the following is the correct order in which the events above occur? QPTRS PTRSQ TRPQS QTPRS

asked Feb 14, 2018 in Operating System by gatecse Boss (16.1k points) | 2.5k views

+2 votes

0 answers

18

Gateforum Tests
Can anybody explain in brief how to solve such numericals.

asked Jan 15, 2018 in CO and Architecture by vishal chugh Active (1.7k points) | 129 views

+1 vote

1 answer

19

Test Series

asked Jan 13, 2018 in CO and Architecture by vishal chugh Active (1.7k points) | 79 views

+2 votes

1 answer

20

Address after Halt instruction
Consider that the memory is byte addressable with size 16 bits, and the program has been loaded starting from memory location (2000)10. What will be the return address saved in the stack, if an interrupt occurs while the CPU has been halted after executing the HALT instruction? I am getting 2018.

asked Jan 2, 2018 in CO and Architecture by Shubhanshu Boss (18k points) | 509 views

+1 vote

1 answer

21

Interrupts
In case of Vectored interrupts,the I/o device send the vector address along with the I/o request or does it sends after it receives ack/INTA from CPU?

asked Dec 10, 2017 in Operating System by rahul sharma 5 Boss (24.5k points) | 90 views

0 votes

1 answer

22

Operating system:- Interrupts
when the interrupt occurs ,then a: process switching may be there b: context saving must be there c: both a and b d.None of these

asked Dec 8, 2017 in Operating System by rahul sharma 5 Boss (24.5k points) | 215 views

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1 answer

23

memory address saved on stack after interrupt
Consider that the memory is byte addressable with size 16 bits, and the program has been loaded starting from memory location (2000)10. What will be the return address saved in the stack, if an interrupt occurs while the CPU has been halted after executing the HALT instruction?

asked Dec 2, 2017 in CO and Architecture by Tuhin Dutta Loyal (9.2k points) | 458 views

+3 votes

3 answers

24

Interrupt
GATE -2009 A CPU generally handles an interrupt by executing an interrupt service routine As soon as an interrupt is raised. By checking the interrupt register at the end of fetch cycle. By checking the interrupt register after finishing the execution of the ... am having confusion between option A and C... For hardware interrupt option A is suitable and for software interrupt option C

asked Oct 26, 2017 in CO and Architecture by #Rahul (307 points) | 378 views

+3 votes

2 answers

25

Non vectored interrupt.
In non vectored interrupt, the address of ISR is a) assigned to fixed memory location b) obtained from interrupt vector table c) none of the above

asked Aug 28, 2017 in CO and Architecture by Xylene Active (3.5k points) | 684 views

0 votes

1 answer

26

NPTEL
Which of the following does not interrupt a running process? 1. A device 2. Timer 3. Power Failure 4. None of the above

asked Aug 23, 2017 in Operating System by gulsanchouhan (249 points) | 185 views

+1 vote

1 answer

27

MadeEasy Subject Test: CO & Architecture - Io Handling
The solution says that the answer should be 80, but applying the formula (x/y)*100, where x is 250 and y is 200 fraction comes out to be greater than 1. Am i making a mistake in interpreting x and y here?

asked Jul 8, 2017 in CO and Architecture by kimaya (49 points) | 274 views

+1 vote

1 answer

28

[COA] I/o Organization
Consider the following statements:- 1. Change program counter value 2. Change page table register context 3. Disable interrupt 4. Initiate I/o on a disk using memory mapped I/o which of the above can be executed in only in system mode? a.) 1,3,4 b)2,3,4 c.)1,2,3 d)2,4,1 Please give valid explanation with your answer.

asked May 27, 2017 in CO and Architecture by rahul sharma 5 Boss (24.5k points) | 244 views

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1 answer

29

[CO}Vectored interrupt
1. In case of vectored interrupt ,the i/o device will send vector address and then using this vector address,the IVT is referred which gives ISR address and then ISR is executed.So,the address that the I/o supplies is not the ISR ... fixed entries for ISR irrespective of vectored/non-vectored intrrupts? Is my understanding correct? Please correct me if i am missing anything?

asked May 18, 2017 in CO and Architecture by rahul sharma 5 Boss (24.5k points) | 432 views

0 votes

1 answer

30

ISRO 2011 -ECE Operating System
Which of the following is not true regarding a preemptive kernel a. If a high priority thread becomes ready to run, low priority thread is preempted b. The kernel checks for the high priority ready to run threads when ever called c. The executing thread is never interrupted d. There are special demands on communication between threads and handling common resources

asked Feb 28, 2017 in Operating System by sh!va Boss (32k points) | 113 views

tags	tag:apple
author	user:martin
title	title:apple
content	content:apple
exclude	-tag:apple
force match	+apple
views	views:100
score	score:10
answers	answers:2
is accepted	isaccepted:true
is closed	isclosed:true

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