Recent questions tagged io-handling

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1

MadeEasy Test Series: CO & Architecture - IO Handling
A CPU scans the status of output I/O device every 20ms. The interface for the I/O device includes two different parts one for status and other for data output. Assume the clock rate of CPU is 8MHz and every instruction takes 10 cycles. What is the time taken(in microseconds) to scan and service the I/O device by CPU? A)4.5 B)3.75 C)1.25 D)2.5

asked Jan 7 in CO & Architecture by Parth Shah Junior (689 points) | 37 views

+1 vote

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Gateforum Test Series: Operating System - Io Handling
Shouldn’t the answer be A but D is provided as an answer

asked Nov 25, 2018 in Operating System by Gupta731 Active (4.8k points) | 101 views

+1 vote

1 answer

3

I/O-COA
I think percentage of processor time consumed should be $\frac{ \,ISR\,time}{ISR\,time+\,Data\,Transfer\,Time}=\frac{100}{100+122}$. Is it correct?

asked Oct 30, 2018 in CO & Architecture by Ayush Upadhyaya Boss (25.3k points) | 83 views

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2 answers

4

Non Vectored Interrupt

asked Oct 21, 2018 in CO & Architecture by Na462 Loyal (8.7k points) | 125 views

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5

Vectored I/O

asked Sep 24, 2018 in CO & Architecture by Na462 Loyal (8.7k points) | 74 views

+2 votes

1 answer

6

I/O operation
Please Explain Every Point :) Ans. All are Correct

asked Aug 13, 2018 in CO & Architecture by Na462 Loyal (8.7k points) | 259 views

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7

MadeEasy Test Series: CO & Architecture - Io Handling
Consider a system employing interrupt driven I/O for a particular device that transfer data at an average of 8 KB/sec on a continuous basis. Consider interrupt processing takes about 100 μsec i.e. time to jump to ISR, execute it and return ... if interrupts occur for every byte is ________. [Assume 1 K = 1024] (Upto 2 decimal places) Ans. 0.81

asked Jul 25, 2018 in CO & Architecture by Na462 Loyal (8.7k points) | 199 views

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1 answer

8

UGCNET-July-2018-II-54
Normally user programs are prevented from handling I/O directly by I/O instructions in them. For CPUs having explicit I/O instructions, such I/O protection is ensured by having the I/O instructions privileged. In a CPU with memory mapped I/O, ... I/O protection is ensured by a hardware trap I/O protection is ensured during system configuration I/O protection is not possible

asked Jul 13, 2018 in Operating System by Pooja Khatri Boss (10.7k points) | 146 views

+1 vote

1 answer

9

I/O Interface
State whether the following statement is TRUE or FALSE and why ? In a microprocessor-based system, if a bus (DMA) request and an interrupt request arrive simultaneously, the microprocessor attends first to the bus request.

asked May 4, 2018 in CO & Architecture by ankitgupta.1729 Boss (10.7k points) | 217 views

+1 vote

1 answer

10

MadeEasy Subject Test: CO & Architecture - Io Handling
The solution says that the answer should be 80, but applying the formula (x/y)*100, where x is 250 and y is 200 fraction comes out to be greater than 1. Am i making a mistake in interpreting x and y here?

asked Jul 8, 2017 in CO & Architecture by kimaya (61 points) | 253 views

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11

MadeEasy Subject Test: CO & Architecture - Io Handling

asked Feb 2, 2017 in CO & Architecture by jatinmittal199510 Active (1.2k points) | 110 views

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2 answers

12

MadeEasy Subject Test: CO & Architecture - Io Handling
A device with data transfer rate of 8 KBps is connected to a CPU. Data is transferred bytewise. Let interrupt overhead be 2 μsec. The byte transfer time between the device interface register and CPU or memory is ... the device under interrupt mode over operating it under program-controlled mode is __________ . (Upto 1 decimal places)

asked Jan 26, 2017 in CO & Architecture by Pankaj Joshi Active (3.1k points) | 209 views

+1 vote

1 answer

13

MadeEasy Subject Test: CO & Architecture - Io Handling

asked Jan 8, 2017 in CO & Architecture by Lucky sunda Active (4.5k points) | 107 views

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1 answer

14

MadeEasy Test Series: CO & Architecture - I/O Handling
#plz check??

asked Nov 28, 2016 in CO & Architecture by Hradesh patel Loyal (7.2k points) | 85 views

+13 votes

4 answers

15

GATE1990-4-ii
State whether the following statements are TRUE or FALSE with reason: The data transfer between memory and $I/O$ devices using programmed $I/O$ is faster than interrupt-driven $I/O$.

asked Nov 24, 2016 in CO & Architecture by makhdoom ghaya Boss (41.1k points) | 1.2k views

+1 vote

1 answer

16

GATE1987-2b
State whether the following statements are TRUE or FALSE: Data transfer between a microprocessor and an $I/O$ device is usually faster in memory-mapped-$I/O$ scheme than in $I/O$-mapped -$I/O$ scheme.

asked Nov 9, 2016 in CO & Architecture by makhdoom ghaya Boss (41.1k points) | 309 views

+1 vote

2 answers

17

GATE1987-2a
State whether the following statements are TRUE or FALSE In a microprocessor-based system, if a bus (DMA) request and an interrupt request arrive sumultaneously, the microprocessor attends first to the bus request.

asked Nov 9, 2016 in CO & Architecture by makhdoom ghaya Boss (41.1k points) | 372 views

0 votes

0 answers

18

Different types of ports and their difference
what is the difference between [1]Serial Port and Parallel Port, [2]Serial port in PC and Serial I/O interface

asked Nov 3, 2016 in CO & Architecture by LavTheRawkstar Active (5.2k points) | 107 views

+1 vote

0 answers

19

MadeEasy Workbook: CO & Architecture - I/O Handling
Q. A processor that communicates with remote terminals over telephone and other communication media in a serial fashion is called A) IO processor B) DMA controller C) Data communication processor D) USART Plz expalin each one???

asked Oct 2, 2016 in CO & Architecture by Hradesh patel Loyal (7.2k points) | 123 views

+2 votes

4 answers

20

ISRO2011-58
In DMA transfer scheme, the transfer scheme other than burst mode is cycle technique stealing technique cycle stealing technique cycle bypass technique

asked Jun 23, 2016 in CO & Architecture by jothee Veteran (115k points) | 1.9k views

+8 votes

3 answers

21

ISRO2011-39
Two control signals in microprocessor which are related to Direct Memory Access (DMA) are INTR & INTA RD & WR S0 & S1 HOLD & HLDA

asked Jun 22, 2016 in CO & Architecture by jothee Veteran (115k points) | 1.8k views

+5 votes

2 answers

22

ISRO2008-36
An interrupt in which the external device supplies its address as well as the interrupt requests is known as vectored interrupt maskable interrupt non maskable interrupt designated interrupt

asked Jun 12, 2016 in CO & Architecture by jothee Veteran (115k points) | 1.8k views

+3 votes

4 answers

23

ISRO-2013-52
Suppose we have variable logical records of lengths of $5$ bytes, $10$ bytes and $25$ bytes while the physical block size in disk is $15$ bytes. What is the maximum and minimum fragmentation seen in bytes? $25$ and $5$ $15$ and $5$ $15$ and $0$ $10$ and $5$

asked May 2, 2016 in Operating System by makhdoom ghaya Boss (41.1k points) | 2.9k views

0 votes

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24

MadeEasy Test Series: CO & Architecture - I/O Handling
Identify the false statements: S1: Separate I/O address space does not necessarily mean that I/O address lines are physically separated. S2: Address decoder is an essential part of I/O interface. a) Only S1 b) Only S2 c) Both S1 and S2 d) Neither S1 nor S2

asked Jan 19, 2016 in CO & Architecture by Sandeep Singh Loyal (7.8k points) | 82 views

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1 answer

25

Direct memory access is used for high-speed I/O devices.
Direct memory access is used for high-speed I/O devices. Why this happens.what is co relation between speed of I/O and DMA transfer becoz anyway DMA is more efficient than other modes such as interrupt driven, so why its not efficient for slower I/O devices?

asked Nov 18, 2015 in CO & Architecture by Anurag_s Loyal (8.2k points) | 568 views

0 votes

1 answer

26

bit rate of video terminal unit
what is bit rate of video terminal unit with 80 character/line , 8 bits/character and horizontal sweep time of 100 micro sec?

asked Oct 7, 2015 in Operating System by monali Junior (619 points) | 407 views

+5 votes

2 answers

27

ISRO2009-78
On receiving an interrupt from an I/O device,the CPU Halts for a predetermined time Branches off to the interrupt service routine after completion of the current instruction Branches off to the interrupt service routine immediately Hands over control of address bus and data bus to the interrupting device

asked Oct 5, 2015 in CO & Architecture by ajit Active (3.3k points) | 3.1k views

+12 votes

2 answers

28

GATE2004-IT-11, ISRO2011-33
What is the bit rate of a video terminal unit with $80$ characters/line, $8$ $\text{bits/character}$ and horizontal sweep time of $100$ $\text{µs}$ (including $20$ $\text{µs}$ of retrace time)? $8$ $\text{Mbps}$ $6.4$ $\text{Mbps}$ $0.8$ $\text{Mbps}$ $0.64$ $\text{Mbps}$

asked Nov 2, 2014 in Operating System by Ishrat Jahan Boss (19.1k points) | 2.6k views

+25 votes

2 answers

29

GATE2006-IT-8
Which of the following DMA transfer modes and interrupt handling mechanisms will enable the highest I/O band-width? Transparent DMA and Polling interrupts Cycle-stealing and Vectored interrupts Block transfer and Vectored interrupts Block transfer and Polling interrupts

asked Oct 31, 2014 in Operating System by Ishrat Jahan Boss (19.1k points) | 3.8k views

+20 votes

4 answers

30

GATE1996-25
A hard disk is connected to a $50$ MHz processor through a DMA controller. Assume that the initial set-up of a DMA transfer takes $1000$ clock cycles for the processor, and assume that the handling of the interrupt at DMA completion requires $500$ clock cycles ... . What fraction of the processor time is consumed by the disk, if the disk is actively transferring $100\%$ of the time?

asked Oct 10, 2014 in CO & Architecture by Kathleen Veteran (59.8k points) | 3k views

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