Dark Mode

Recent questions tagged io-handling

2 votes

1 answer

1

Applied Course | Mock GATE | Test 1 | Question: 62
Consider a $32$ bit, $10$ MIPS processor with an interrupt driven interface. Suppose a hard disk has a $16$ bit data bus and is connected to the processor and its transfer rate is $50 \:KB$ per second. ... instructions per second) $256000$ instructions per second $512000$ instructions per second $1024000$ instructions per second None of the above

Applied Course asked in CO and Architecture Jan 16, 2019

by Applied Course

328 views

0 votes

0 answers

2

ACE Test-4(GCO-2)
Correct Statements ??? S1 : Generally I/O mapped I/O technique is used to connect more number of I/O devices then memory mapped I/O technique. S2 : Processor generates memory read (MRD) and memory write (MWR) control signals while communication with I/ ... I/O, the valuable memory space address is wasted due to the utilization of this memory space address to the I/O devices.

arya_stark asked in CO and Architecture Jan 15, 2019

393 views

0 votes

2 answers

3

MadeEasy Test Series: CO & Architecture - IO Handling
A CPU scans the status of output I/O device every 20ms. The interface for the I/O device includes two different parts one for status and other for data output. Assume the clock rate of CPU is 8MHz and every instruction takes 10 cycles. What is the time taken(in microseconds) to scan and service the I/O device by CPU? A)4.5 B)3.75 C)1.25 D)2.5

Parth Shah asked in CO and Architecture Jan 7, 2019

513 views

1 vote

0 answers

4

Gateforum Test Series: Operating System - Io Handling
Shouldn’t the answer be A but D is provided as an answer

Gupta731 asked in Operating System Nov 25, 2018

368 views

1 vote

1 answer

5

I/O-COA
I think percentage of processor time consumed should be $\frac{ \,ISR\,time}{ISR\,time+\,Data\,Transfer\,Time}=\frac{100}{100+122}$. Is it correct?

Ayush Upadhyaya asked in CO and Architecture Oct 30, 2018

by Ayush Upadhyaya

874 views

0 votes

2 answers

6

Non Vectored Interrupt

Na462 asked in CO and Architecture Oct 21, 2018

by Na462

1.2k views

1 vote

1 answer

7

Na462 asked in CO and Architecture Sep 24, 2018

by Na462

492 views

3 votes

1 answer

8

I/O operation
Please Explain Every Point :) Ans. All are Correct

Na462 asked in CO and Architecture Aug 13, 2018

by Na462

1.4k views

2 votes

5 answers

9

MadeEasy Test Series: CO & Architecture - Io Handling
Consider a system employing interrupt driven I/O for a particular device that transfer data at an average of 8 KB/sec on a continuous basis. Consider interrupt processing takes about 100 μsec i.e. time to jump to ISR, execute it and return ... if interrupts occur for every byte is ________. [Assume 1 K = 1024] (Upto 2 decimal places) Ans. 0.81

Na462 asked in CO and Architecture Jul 25, 2018

by Na462

1.6k views

0 votes

1 answer

10

UGC NET CSE | July 2018 | Part 2 | Question: 54
Normally user programs are prevented from handling I/O directly by I/O instructions in them. For CPUs having explicit I/O instructions, such I/O protection is ensured by having the I/O instructions privileged. In a CPU with ... protection is ensured by a hardware trap I/O protection is ensured during system configuration I/O protection is not possible

Pooja Khatri asked in Operating System Jul 13, 2018

by Pooja Khatri

858 views

0 votes

0 answers

11

ISI Mtech exam -2016
Please help me with this question.. The CPU of a system having an execution rate of 1 million instructions per second needs 4 machine cycles on an average for executing an instruction. On an average, 50% of the cycles use memory bus. For ... transferring one byte involves 4 operations: in-status, check-status, branch and read/write in memory, each requiring one machine cycle.

Vikram Saurabh asked in CO and Architecture May 4, 2018

by Vikram Saurabh

340 views

1 vote

2 answers

12

ISRO2018-65
Of the following, which best characterizes computers that use memory-mapped $I/O$? The computer provides special instructions for manipulating $I/O$ ports $I/O$ ports are placed at addresses on the bus and are accessed just like other memory locations ... address register and call channel to perform the operation $I/O$ can be performed only when memory management hardware is turned on

Arjun asked in CO and Architecture Apr 22, 2018

by Arjun

2.7k views

1 vote

1 answer

13

status Register & I/o
What is the work of status register in I/O operation ?

Sunil8860 asked in CO and Architecture Aug 9, 2017

827 views

2 votes

1 answer

14

MadeEasy Subject Test: CO & Architecture - Io Handling
The solution says that the answer should be 80, but applying the formula (x/y)*100, where x is 250 and y is 200 fraction comes out to be greater than 1. Am i making a mistake in interpreting x and y here?

kimaya asked in CO and Architecture Jul 8, 2017

by kimaya

574 views

0 votes

0 answers

15

MadeEasy Subject Test: CO & Architecture - Io Handling

jatinmittal199510 asked in CO and Architecture Feb 2, 2017

by jatinmittal199510

276 views

1 vote

5 answers

16

MadeEasy Subject Test: CO & Architecture - Io Handling
A device with data transfer rate of 8 KBps is connected to a CPU. Data is transferred bytewise. Let interrupt overhead be 2 μsec. The byte transfer time between the device interface register and CPU or memory is ... the device under interrupt mode over operating it under program-controlled mode is __________ . (Upto 1 decimal places)

Pankaj Joshi asked in CO and Architecture Jan 26, 2017

by Pankaj Joshi

1.8k views

1 vote

1 answer

17

MadeEasy Subject Test: CO & Architecture - Io Handling

Lucky sunda asked in CO and Architecture Jan 8, 2017

289 views

0 votes

2 answers

18

MadeEasy Test Series: CO & Architecture - I/O Handling
#plz check??

Hradesh patel asked in CO and Architecture Nov 28, 2016

by Hradesh patel

327 views

3 votes

2 answers

19

Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 23
A hard disk is connected to a $2$ GHz processor through a DMA controller which works in burst mode. The initial set up of a DMA transfer takes $1000$ ... is $16$ KB. Then, the fraction of CPU time free if the disk is transferring data is _______%.

Bikram asked in CO and Architecture Nov 25, 2016

by Bikram

392 views

0 votes

2 answers

20

Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 17
The fastest mode of data transfer is: Programmable I/O Interrupt I/O DMA Both A and B

Bikram asked in CO and Architecture Nov 25, 2016

by Bikram

164 views

19 votes

4 answers

21

GATE CSE 1990 | Question: 4-ii
State whether the following statements are TRUE or FALSE with reason: The data transfer between memory and I/O devices using programmed I/O is faster than interrupt-driven I/O.

makhdoom ghaya asked in CO and Architecture Nov 24, 2016

by makhdoom ghaya

6.0k views

2 votes

3 answers

22

GATE CSE 1987 | Question: 2b
State whether the following statements are TRUE or FALSE: Data transfer between a microprocessor and an I/O device is usually faster in memory-mapped-I/O scheme than in I/O-mapped -I/O scheme.

makhdoom ghaya asked in CO and Architecture Nov 9, 2016

by makhdoom ghaya

1.2k views

5 votes

3 answers

23

GATE CSE 1987 | Question: 2a
State whether the following statements are TRUE or FALSE In a microprocessor-based system, if a bus (DMA) request and an interrupt request arrive sumultaneously, the microprocessor attends first to the bus request.

makhdoom ghaya asked in CO and Architecture Nov 9, 2016

by makhdoom ghaya

1.7k views

0 votes

0 answers

24

Different types of ports and their difference
what is the difference between [1]Serial Port and Parallel Port, [2]Serial port in PC and Serial I/O interface

LavTheRawkstar asked in CO and Architecture Nov 3, 2016

by LavTheRawkstar

241 views

1 vote

0 answers

25

MadeEasy Workbook: CO & Architecture - I/O Handling
Q. A processor that communicates with remote terminals over telephone and other communication media in a serial fashion is called A) IO processor B) DMA controller C) Data communication processor D) USART Plz expalin each one???

Hradesh patel asked in CO and Architecture Oct 2, 2016

by Hradesh patel

436 views

4 votes

1 answer

26

input-output
Consider a system employing interrupt-driven I/O for a particular device that transfers data at an average of 8 KB/s on a continuous basis. Assume that interrupt processing takes about 100 microsecond (i.e., the time to jump to the interrupt service routine (ISR), ... by this I/O device if it interrupts for every byte. Is it same as percentage of time CPU is in blocked state ?

saurabh rai asked in CO and Architecture Sep 1, 2016

5.4k views

3 votes

5 answers

27

ISRO2011-58
In DMA transfer scheme, the transfer scheme other than burst mode is cycle technique stealing technique cycle stealing technique cycle bypass technique

go_editor asked in CO and Architecture Jun 23, 2016

2.8k views

9 votes

4 answers

28

ISRO2011-39
Two control signals in microprocessor which are related to Direct Memory Access (DMA) are INTR & INTA RD & WR S0 & S1 HOLD & HLDA

go_editor asked in CO and Architecture Jun 22, 2016

5.2k views

6 votes

4 answers

29

ISRO2008-36
An interrupt in which the external device supplies its address as well as the interrupt requests is known as vectored interrupt maskable interrupt non maskable interrupt designated interrupt

go_editor asked in CO and Architecture Jun 12, 2016

4.3k views

3 votes

4 answers

30

ISRO-2013-52
Suppose we have variable logical records of lengths of $5$ bytes, $10$ bytes and $25$ bytes while the physical block size in disk is $15$ bytes. What is the maximum and minimum fragmentation seen in bytes? $25$ and $5$ $15$ and $5$ $15$ and $0$ $10$ and $5$

makhdoom ghaya asked in Operating System May 2, 2016

by makhdoom ghaya

5.8k views

Page:

Recent questions tagged io-handling