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Recent questions tagged io-handling
0
votes
1
answer
1
self doubt
Can Interrupt-Driven I/O be memory mapped? Polling is memory mapped or IO mapped?
Rutuja7
asked
in
CO and Architecture
Mar 7
by
Rutuja7
118
views
co-and-architecture
io-handling
4
votes
1
answer
2
Applied Course | Mock GATE | Test 1 | Question: 62
Consider a $32$ bit, $10$ MIPS processor with an interrupt driven interface. Suppose a hard disk has a $16$ bit data bus and is connected to the processor and its transfer rate is $50 \:KB$ per second. ... instructions per second) $256000$ instructions per second $512000$ instructions per second $1024000$ instructions per second None of the above
Applied Course
asked
in
CO and Architecture
Jan 16, 2019
by
Applied Course
469
views
applied-course-2019-mock1
io-handling
co-and-architecture
interrupts
0
votes
1
answer
3
ACE Test-4(GCO-2)
Correct Statements ??? S1 : Generally I/O mapped I/O technique is used to connect more number of I/O devices then memory mapped I/O technique. S2 : Processor generates memory read (MRD) and memory write (MWR) control signals while communication with I/ ... I/O, the valuable memory space address is wasted due to the utilization of this memory space address to the I/O devices.
arya_stark
asked
in
CO and Architecture
Jan 15, 2019
by
arya_stark
502
views
co-and-architecture
io-organization
io-handling
0
votes
2
answers
4
MadeEasy Test Series: CO & Architecture - IO Handling
A CPU scans the status of output I/O device every 20ms. The interface for the I/O device includes two different parts one for status and other for data output. Assume the clock rate of CPU is 8MHz and every instruction takes 10 cycles. What is the time taken(in microseconds) to scan and service the I/O device by CPU? A)4.5 B)3.75 C)1.25 D)2.5
Parth Shah
asked
in
CO and Architecture
Jan 7, 2019
by
Parth Shah
749
views
made-easy-test-series
co-and-architecture
io-handling
1
vote
1
answer
5
Gateforum Test Series: Operating System - Io Handling
Shouldn’t the answer be A but D is provided as an answer
Gupta731
asked
in
Operating System
Nov 25, 2018
by
Gupta731
458
views
gateforum-test-series
operating-system
io-handling
1
vote
1
answer
6
I/O-COA
I think percentage of processor time consumed should be $\frac{ \,ISR\,time}{ISR\,time+\,Data\,Transfer\,Time}=\frac{100}{100+122}$. Is it correct?
Ayush Upadhyaya
asked
in
CO and Architecture
Oct 30, 2018
by
Ayush Upadhyaya
986
views
co-and-architecture
interrupts
io-handling
numerical-answers
2
votes
2
answers
7
Non Vectored Interrupt
Na462
asked
in
CO and Architecture
Oct 21, 2018
by
Na462
1.4k
views
interrupts
co-and-architecture
io-handling
1
vote
1
answer
8
Vectored I/O
Na462
asked
in
CO and Architecture
Sep 24, 2018
by
Na462
614
views
co-and-architecture
interrupts
io-handling
4
votes
1
answer
9
I/O operation
Please Explain Every Point :) Ans. All are Correct
Na462
asked
in
CO and Architecture
Aug 13, 2018
by
Na462
1.6k
views
co-and-architecture
interrupts
io-handling
3
votes
5
answers
10
MadeEasy Test Series: CO & Architecture - Io Handling
Consider a system employing interrupt driven I/O for a particular device that transfer data at an average of 8 KB/sec on a continuous basis. Consider interrupt processing takes about 100 μsec i.e. time to jump to ISR, execute it and return ... if interrupts occur for every byte is ________. [Assume 1 K = 1024] (Upto 2 decimal places) Ans. 0.81
Na462
asked
in
CO and Architecture
Jul 25, 2018
by
Na462
1.9k
views
co-and-architecture
interrupts
made-easy-test-series
io-handling
0
votes
1
answer
11
UGC NET CSE | July 2018 | Part 2 | Question: 54
Normally user programs are prevented from handling I/O directly by I/O instructions in them. For CPUs having explicit I/O instructions, such I/O protection is ensured by having the I/O instructions privileged. In a CPU with ... protection is ensured by a hardware trap I/O protection is ensured during system configuration I/O protection is not possible
Pooja Khatri
asked
in
Operating System
Jul 13, 2018
by
Pooja Khatri
975
views
ugcnetcse-july2018-paper2
operating-system
io-handling
0
votes
0
answers
12
ISI Mtech exam -2016
Please help me with this question.. The CPU of a system having an execution rate of 1 million instructions per second needs 4 machine cycles on an average for executing an instruction. On an average, 50% of the cycles use memory bus. For ... transferring one byte involves 4 operations: in-status, check-status, branch and read/write in memory, each requiring one machine cycle.
Vikram Saurabh
asked
in
CO and Architecture
May 4, 2018
by
Vikram Saurabh
372
views
userisi2016
usermod
dma
io-handling
3
votes
2
answers
13
ISRO2018-65
Of the following, which best characterizes computers that use memory-mapped $\text{I/O}?$ The computer provides special instructions for manipulating $\text{I/O}$ ports $\text{I/O}$ ports are placed at addresses on the bus and are accessed just like ... register and call channel to perform the operation $\text{I/O}$ can be performed only when memory management hardware is turned on
Arjun
asked
in
CO and Architecture
Apr 22, 2018
by
Arjun
2.9k
views
isro2018
co-and-architecture
io-handling
1
vote
1
answer
14
status Register & I/o
What is the work of status register in I/O operation ?
Sunil8860
asked
in
CO and Architecture
Aug 9, 2017
by
Sunil8860
1.2k
views
co-and-architecture
io-handling
registers
2
votes
1
answer
15
MadeEasy Subject Test: CO & Architecture - Io Handling
The solution says that the answer should be 80, but applying the formula (x/y)*100, where x is 250 and y is 200 fraction comes out to be greater than 1. Am i making a mistake in interpreting x and y here?
kimaya
asked
in
CO and Architecture
Jul 8, 2017
by
kimaya
626
views
co-and-architecture
made-easy-test-series
interrupts
io-handling
0
votes
0
answers
16
MadeEasy Subject Test: CO & Architecture - Io Handling
jatinmittal199510
asked
in
CO and Architecture
Feb 2, 2017
by
jatinmittal199510
329
views
made-easy-test-series
co-and-architecture
io-handling
1
vote
5
answers
17
MadeEasy Subject Test: CO & Architecture - Io Handling
A device with data transfer rate of 8 KBps is connected to a CPU. Data is transferred bytewise. Let interrupt overhead be 2 μsec. The byte transfer time between the device interface register and CPU or memory is ... the device under interrupt mode over operating it under program-controlled mode is __________ . (Upto 1 decimal places)
Pankaj Joshi
asked
in
CO and Architecture
Jan 26, 2017
by
Pankaj Joshi
2.1k
views
made-easy-test-series
co-and-architecture
io-handling
1
vote
1
answer
18
MadeEasy Subject Test: CO & Architecture - Io Handling
Lucky sunda
asked
in
CO and Architecture
Jan 8, 2017
by
Lucky sunda
339
views
made-easy-test-series
co-and-architecture
io-handling
0
votes
2
answers
19
MadeEasy Test Series: CO & Architecture - I/O Handling
#plz check??
Hradesh patel
asked
in
CO and Architecture
Nov 28, 2016
by
Hradesh patel
398
views
made-easy-test-series
co-and-architecture
io-handling
3
votes
2
answers
20
Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 23
A hard disk is connected to a $2$ GHz processor through a DMA controller which works in burst mode. The initial set up of a DMA transfer takes $1000$ ... is $16$ KB. Then, the fraction of CPU time free if the disk is transferring data is _______%.
Bikram
asked
in
CO and Architecture
Nov 25, 2016
by
Bikram
593
views
tbb-coa-1
co-and-architecture
numerical-answers
io-handling
dma
0
votes
2
answers
21
Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 17
The fastest mode of data transfer is: Programmable I/O Interrupt I/O DMA Both A and B
Bikram
asked
in
CO and Architecture
Nov 25, 2016
by
Bikram
272
views
tbb-coa-1
co-and-architecture
io-handling
interrupts
dma
19
votes
4
answers
22
GATE CSE 1990 | Question: 4-ii
State whether the following statements are TRUE or FALSE with reason: The data transfer between memory and I/O devices using programmed I/O is faster than interrupt-driven I/O.
makhdoom ghaya
asked
in
CO and Architecture
Nov 24, 2016
by
makhdoom ghaya
6.6k
views
gate1990
true-false
co-and-architecture
io-handling
interrupts
2
votes
3
answers
23
GATE CSE 1987 | Question: 2b
State whether the following statements are TRUE or FALSE: Data transfer between a microprocessor and an I/O device is usually faster in memory-mapped-I/O scheme than in I/O-mapped -I/O scheme.
makhdoom ghaya
asked
in
CO and Architecture
Nov 9, 2016
by
makhdoom ghaya
1.5k
views
gate1987
co-and-architecture
io-handling
true-false
5
votes
3
answers
24
GATE CSE 1987 | Question: 2a
State whether the following statements are TRUE or FALSE In a microprocessor-based system, if a bus (DMA) request and an interrupt request arrive sumultaneously, the microprocessor attends first to the bus request.
makhdoom ghaya
asked
in
CO and Architecture
Nov 9, 2016
by
makhdoom ghaya
2.1k
views
gate1987
co-and-architecture
interrupts
io-handling
true-false
0
votes
0
answers
25
Different types of ports and their difference
what is the difference between [1]Serial Port and Parallel Port, [2]Serial port in PC and Serial I/O interface
LavTheRawkstar
asked
in
CO and Architecture
Nov 3, 2016
by
LavTheRawkstar
285
views
co-and-architecture
io-handling
1
vote
0
answers
26
MadeEasy Workbook: CO & Architecture - I/O Handling
Q. A processor that communicates with remote terminals over telephone and other communication media in a serial fashion is called A) IO processor B) DMA controller C) Data communication processor D) USART Plz expalin each one???
Hradesh patel
asked
in
CO and Architecture
Oct 2, 2016
by
Hradesh patel
470
views
made-easy-booklet
co-and-architecture
io-handling
4
votes
1
answer
27
input-output
Consider a system employing interrupt-driven I/O for a particular device that transfers data at an average of 8 KB/s on a continuous basis. Assume that interrupt processing takes about 100 microsecond (i.e., the time to jump to the interrupt service routine (ISR), ... by this I/O device if it interrupts for every byte. Is it same as percentage of time CPU is in blocked state ?
saurabh rai
asked
in
CO and Architecture
Sep 1, 2016
by
saurabh rai
6.2k
views
co-and-architecture
interrupts
io-handling
4
votes
5
answers
28
ISRO2011-58
In DMA transfer scheme, the transfer scheme other than burst mode is cycle technique stealing technique cycle stealing technique cycle bypass technique
go_editor
asked
in
CO and Architecture
Jun 23, 2016
by
go_editor
3.1k
views
isro2011
co-and-architecture
io-handling
dma
11
votes
4
answers
29
ISRO2011-39
Two control signals in microprocessor which are related to Direct Memory Access (DMA) are $\textsf{INTR & INTA}$ $\textsf{RD & WR}$ $\textsf{S0 & S1}$ $\textsf{HOLD & HLDA}$
go_editor
asked
in
CO and Architecture
Jun 22, 2016
by
go_editor
5.6k
views
isro2011
co-and-architecture
io-handling
dma
6
votes
4
answers
30
ISRO2008-36
An interrupt in which the external device supplies its address as well as the interrupt requests is known as vectored interrupt maskable interrupt non maskable interrupt designated interrupt
go_editor
asked
in
CO and Architecture
Jun 12, 2016
by
go_editor
4.5k
views
isro2008
co-and-architecture
io-handling
interrupts
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