Recent questions tagged io-handling

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1

ACE Test-4(GCO-2)
Correct Statements ??? S1 : Generally I/O mapped I/O technique is used to connect more number of I/O devices then memory mapped I/O technique. S2 : Processor generates memory read (MRD) and memory write (MWR) control signals while communication with I/ ... I/O, the valuable memory space address is wasted due to the utilization of this memory space address to the I/O devices.

asked Jan 15 in CO & Architecture by arya_stark Active (1.6k points) | 30 views

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2

MadeEasy Test Series: CO & Architecture - IO Handling
A CPU scans the status of output I/O device every 20ms. The interface for the I/O device includes two different parts one for status and other for data output. Assume the clock rate of CPU is 8MHz and every instruction takes 10 cycles. What is the time taken(in microseconds) to scan and service the I/O device by CPU? A)4.5 B)3.75 C)1.25 D)2.5

asked Jan 7 in CO & Architecture by Parth Shah Junior (667 points) | 39 views

+1 vote

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3

Gateforum Test Series: Operating System - Io Handling
Shouldn’t the answer be A but D is provided as an answer

asked Nov 25, 2018 in Operating System by Gupta731 Active (4.5k points) | 103 views

+1 vote

1 answer

4

I/O-COA
I think percentage of processor time consumed should be $\frac{ \,ISR\,time}{ISR\,time+\,Data\,Transfer\,Time}=\frac{100}{100+122}$. Is it correct?

asked Oct 30, 2018 in CO & Architecture by Ayush Upadhyaya Boss (24.5k points) | 101 views

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2 answers

5

Non Vectored Interrupt

asked Oct 21, 2018 in CO & Architecture by Na462 Loyal (6.6k points) | 145 views

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6

Vectored I/O

asked Sep 24, 2018 in CO & Architecture by Na462 Loyal (6.6k points) | 81 views

+2 votes

1 answer

7

I/O operation
Please Explain Every Point :) Ans. All are Correct

asked Aug 13, 2018 in CO & Architecture by Na462 Loyal (6.6k points) | 280 views

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1 answer

8

MadeEasy Test Series: CO & Architecture - Io Handling
Consider a system employing interrupt driven I/O for a particular device that transfer data at an average of 8 KB/sec on a continuous basis. Consider interrupt processing takes about 100 μsec i.e. time to jump to ISR, execute it and return ... if interrupts occur for every byte is ________. [Assume 1 K = 1024] (Upto 2 decimal places) Ans. 0.81

asked Jul 25, 2018 in CO & Architecture by Na462 Loyal (6.6k points) | 229 views

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1 answer

9

UGCNET-July-2018-II-54
Normally user programs are prevented from handling I/O directly by I/O instructions in them. For CPUs having explicit I/O instructions, such I/O protection is ensured by having the I/O instructions privileged. In a CPU with memory mapped I/O, ... I/O protection is ensured by a hardware trap I/O protection is ensured during system configuration I/O protection is not possible

asked Jul 13, 2018 in Operating System by Pooja Khatri Boss (10.7k points) | 209 views

+1 vote

1 answer

10

I/O Interface
State whether the following statement is TRUE or FALSE and why ? In a microprocessor-based system, if a bus (DMA) request and an interrupt request arrive simultaneously, the microprocessor attends first to the bus request.

asked May 4, 2018 in CO & Architecture by ankitgupta.1729 Boss (13.2k points) | 240 views

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11

ISI Mtech exam -2016
Please help me with this question.. The CPU of a system having an execution rate of 1 million instructions per second needs 4 machine cycles on an average for executing an instruction. On an average, 50% of the cycles use memory bus. For ... transferring one byte involves 4 operations: in-status, check-status, branch and read/write in memory, each requiring one machine cycle.

asked May 4, 2018 in CO & Architecture by Vikram Saurabh (5 points) | 96 views

+1 vote

1 answer

12

status Register & I/o
What is the work of status register in I/O operation ?

asked Aug 9, 2017 in CO & Architecture by Sunil8860 (-113 points) | 87 views

+1 vote

1 answer

13

MadeEasy Subject Test: CO & Architecture - Io Handling
The solution says that the answer should be 80, but applying the formula (x/y)*100, where x is 250 and y is 200 fraction comes out to be greater than 1. Am i making a mistake in interpreting x and y here?

asked Jul 8, 2017 in CO & Architecture by kimaya (49 points) | 262 views

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14

MadeEasy Subject Test: CO & Architecture - Io Handling

asked Feb 2, 2017 in CO & Architecture by jatinmittal199510 Active (1.2k points) | 113 views

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3 answers

15

MadeEasy Subject Test: CO & Architecture - Io Handling
A device with data transfer rate of 8 KBps is connected to a CPU. Data is transferred bytewise. Let interrupt overhead be 2 μsec. The byte transfer time between the device interface register and CPU or memory is ... the device under interrupt mode over operating it under program-controlled mode is __________ . (Upto 1 decimal places)

asked Jan 26, 2017 in CO & Architecture by Pankaj Joshi Active (2.6k points) | 238 views

+1 vote

1 answer

16

MadeEasy Subject Test: CO & Architecture - Io Handling

asked Jan 8, 2017 in CO & Architecture by Lucky sunda Active (4.4k points) | 112 views

0 votes

1 answer

17

MadeEasy Test Series: CO & Architecture - I/O Handling
#plz check??

asked Nov 28, 2016 in CO & Architecture by Hradesh patel Loyal (6.2k points) | 86 views

+13 votes

4 answers

18

GATE1990-4-ii
State whether the following statements are TRUE or FALSE with reason: The data transfer between memory and $I/O$ devices using programmed $I/O$ is faster than interrupt-driven $I/O$.

asked Nov 24, 2016 in CO & Architecture by makhdoom ghaya Boss (29.3k points) | 1.2k views

+1 vote

1 answer

19

GATE1987-2b
State whether the following statements are TRUE or FALSE: Data transfer between a microprocessor and an $I/O$ device is usually faster in memory-mapped-$I/O$ scheme than in $I/O$-mapped -$I/O$ scheme.

asked Nov 9, 2016 in CO & Architecture by makhdoom ghaya Boss (29.3k points) | 319 views

+1 vote

2 answers

20

GATE1987-2a
State whether the following statements are TRUE or FALSE In a microprocessor-based system, if a bus (DMA) request and an interrupt request arrive sumultaneously, the microprocessor attends first to the bus request.

asked Nov 9, 2016 in CO & Architecture by makhdoom ghaya Boss (29.3k points) | 381 views

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0 answers

21

Different types of ports and their difference
what is the difference between [1]Serial Port and Parallel Port, [2]Serial port in PC and Serial I/O interface

asked Nov 3, 2016 in CO & Architecture by LavTheRawkstar Active (3.7k points) | 110 views

+1 vote

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22

MadeEasy Workbook: CO & Architecture - I/O Handling
Q. A processor that communicates with remote terminals over telephone and other communication media in a serial fashion is called A) IO processor B) DMA controller C) Data communication processor D) USART Plz expalin each one???

asked Oct 2, 2016 in CO & Architecture by Hradesh patel Loyal (6.2k points) | 128 views

+2 votes

4 answers

23

ISRO2011-58
In DMA transfer scheme, the transfer scheme other than burst mode is cycle technique stealing technique cycle stealing technique cycle bypass technique

asked Jun 23, 2016 in CO & Architecture by jothee Veteran (96.1k points) | 2k views

+8 votes

3 answers

24

ISRO2011-39
Two control signals in microprocessor which are related to Direct Memory Access (DMA) are INTR & INTA RD & WR S0 & S1 HOLD & HLDA

asked Jun 22, 2016 in CO & Architecture by jothee Veteran (96.1k points) | 1.9k views

+5 votes

2 answers

25

ISRO2008-36
An interrupt in which the external device supplies its address as well as the interrupt requests is known as vectored interrupt maskable interrupt non maskable interrupt designated interrupt

asked Jun 12, 2016 in CO & Architecture by jothee Veteran (96.1k points) | 1.9k views

+3 votes

4 answers

26

ISRO-2013-52
Suppose we have variable logical records of lengths of $5$ bytes, $10$ bytes and $25$ bytes while the physical block size in disk is $15$ bytes. What is the maximum and minimum fragmentation seen in bytes? $25$ and $5$ $15$ and $5$ $15$ and $0$ $10$ and $5$

asked May 2, 2016 in Operating System by makhdoom ghaya Boss (29.3k points) | 2.9k views

0 votes

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27

MadeEasy Test Series: CO & Architecture - I/O Handling
Identify the false statements: S1: Separate I/O address space does not necessarily mean that I/O address lines are physically separated. S2: Address decoder is an essential part of I/O interface. a) Only S1 b) Only S2 c) Both S1 and S2 d) Neither S1 nor S2

asked Jan 19, 2016 in CO & Architecture by Sandeep Singh Loyal (7.1k points) | 84 views

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1 answer

28

Direct memory access is used for high-speed I/O devices.
Direct memory access is used for high-speed I/O devices. Why this happens.what is co relation between speed of I/O and DMA transfer becoz anyway DMA is more efficient than other modes such as interrupt driven, so why its not efficient for slower I/O devices?

asked Nov 18, 2015 in CO & Architecture by Anurag_s Loyal (8.1k points) | 578 views

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1 answer

29

bit rate of video terminal unit
what is bit rate of video terminal unit with 80 character/line , 8 bits/character and horizontal sweep time of 100 micro sec?

asked Oct 7, 2015 in Operating System by monali (357 points) | 415 views

+5 votes

2 answers

30

ISRO2009-78
On receiving an interrupt from an I/O device,the CPU Halts for a predetermined time Branches off to the interrupt service routine after completion of the current instruction Branches off to the interrupt service routine immediately Hands over control of address bus and data bus to the interrupting device

asked Oct 5, 2015 in CO & Architecture by ajit Active (2.3k points) | 3.2k views

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