menu
search
Log In

GO Book for GATECSE 2022GATE Overflow Book for GATE CSE 2022

Quick search syntax
tags tag:apple
author user:martin
title title:apple
content content:apple
exclude -tag:apple
force match +apple
views views:100
score score:10
answers answers:2
is accepted isaccepted:true
is closed isclosed:true

Subjects


GATE Overflow
Recent questions tagged io-handling

Network Sites

 GO Mechanical
 GO Electrical
 GO Electronics
 GO Civil
 CSE Doubts

Recent questions tagged io-handling

0 votes
0 answers
1
ACE Test-4(GCO-2)
Correct Statements ??? S1 : Generally I/O mapped I/O technique is used to connect more number of I/O devices then memory mapped I/O technique. S2 : Processor generates memory read (MRD) and memory write (MWR) control signals while communication with I/ ... I/O, the valuable memory space address is wasted due to the utilization of this memory space address to the I/O devices.
Correct Statements ??? S1 : Generally I/O mapped I/O technique is used to connect more number of I/O devices then memory mapped I/O technique. S2 : Processor generates memory read (MRD) and memory write (MWR) control signals while communication with I/O devices in ... /O mapped I/O, the valuable memory space address is wasted due to the utilization of this memory space address to the I/O devices.
asked Jan 15, 2019 in CO and Architecture arya_stark 235 views
0 votes
2 answers
2
MadeEasy Test Series: CO & Architecture - IO Handling
A CPU scans the status of output I/O device every 20ms. The interface for the I/O device includes two different parts one for status and other for data output. Assume the clock rate of CPU is 8MHz and every instruction takes 10 cycles. What is the time taken(in microseconds) to scan and service the I/O device by CPU? A)4.5 B)3.75 C)1.25 D)2.5
A CPU scans the status of output I/O device every 20ms. The interface for the I/O device includes two different parts one for status and other for data output. Assume the clock rate of CPU is 8MHz and every instruction takes 10 cycles. What is the time taken(in microseconds) to scan and service the I/O device by CPU? A)4.5 B)3.75 C)1.25 D)2.5
asked Jan 7, 2019 in CO and Architecture Parth Shah 287 views
1 vote
1 answer
4
I/O-COA
I think percentage of processor time consumed should be $\frac{ \,ISR\,time}{ISR\,time+\,Data\,Transfer\,Time}=\frac{100}{100+122}$. Is it correct?
I think percentage of processor time consumed should be $\frac{ \,ISR\,time}{ISR\,time+\,Data\,Transfer\,Time}=\frac{100}{100+122}$. Is it correct?
asked Oct 30, 2018 in CO and Architecture Ayush Upadhyaya 613 views
0 votes
2 answers
5
Non Vectored Interrupt
asked Oct 21, 2018 in CO and Architecture Na462 617 views
1 vote
1 answer
6
Vectored I/O
asked Sep 24, 2018 in CO and Architecture Na462 297 views
3 votes
1 answer
7
I/O operation
Please Explain Every Point :) Ans. All are Correct
Please Explain Every Point :) Ans. All are Correct
asked Aug 13, 2018 in CO and Architecture Na462 952 views
1 vote
5 answers
8
MadeEasy Test Series: CO & Architecture - Io Handling
Consider a system employing interrupt driven I/O for a particular device that transfer data at an average of 8 KB/sec on a continuous basis. Consider interrupt processing takes about 100 μsec i.e. time to jump to ISR, execute it and return ... if interrupts occur for every byte is ________. [Assume 1 K = 1024] (Upto 2 decimal places) Ans. 0.81
Consider a system employing interrupt driven I/O for a particular device that transfer data at an average of 8 KB/sec on a continuous basis. Consider interrupt processing takes about 100 μsec i.e. time to jump to ISR, execute it and return to main program. The fraction of processor ... I/O device if interrupts occur for every byte is ________. [Assume 1 K = 1024] (Upto 2 decimal places) Ans. 0.81
asked Jul 25, 2018 in CO and Architecture Na462 972 views
0 votes
1 answer
9
UGCNET-July-2018-II: 54
Normally user programs are prevented from handling I/O directly by I/O instructions in them. For CPUs having explicit I/O instructions, such I/O protection is ensured by having the I/O instructions privileged. In a CPU with memory mapped I/O, ... I/O protection is ensured by a hardware trap I/O protection is ensured during system configuration I/O protection is not possible
Normally user programs are prevented from handling I/O directly by I/O instructions in them. For CPUs having explicit I/O instructions, such I/O protection is ensured by having the I/O instructions privileged. In a CPU with memory mapped I/O, there is no ... routines I/O protection is ensured by a hardware trap I/O protection is ensured during system configuration I/O protection is not possible
asked Jul 13, 2018 in Operating System Pooja Khatri 607 views
1 vote
1 answer
10
I/O Interface
State whether the following statement is TRUE or FALSE and why ? In a microprocessor-based system, if a bus (DMA) request and an interrupt request arrive simultaneously, the microprocessor attends first to the bus request.
State whether the following statement is TRUE or FALSE and why ? In a microprocessor-based system, if a bus (DMA) request and an interrupt request arrive simultaneously, the microprocessor attends first to the bus request.
asked May 4, 2018 in CO and Architecture ankitgupta.1729 577 views
0 votes
0 answers
11
ISI Mtech exam -2016
Please help me with this question.. The CPU of a system having an execution rate of 1 million instructions per second needs 4 machine cycles on an average for executing an instruction. On an average, 50% of the cycles use memory bus. For ... transferring one byte involves 4 operations: in-status, check-status, branch and read/write in memory, each requiring one machine cycle.
Please help me with this question.. The CPU of a system having an execution rate of 1 million instructions per second needs 4 machine cycles on an average for executing an instruction. On an average, 50% of the cycles use memory bus. For execution of the ... that transferring one byte involves 4 operations: in-status, check-status, branch and read/write in memory, each requiring one machine cycle.
asked May 4, 2018 in CO and Architecture Vikram Saurabh 235 views
1 vote
2 answers
12
ISRO2018-65
Of the following, which best characterizes computers that use memory-mapped $I/O$? The computer provides special instructions for manipulating $I/O$ ports $I/O$ ports are placed at addresses on the bus and are accessed just like other memory locations ... address register and call channel to perform the operation $I/O$ can be performed only when memory management hardware is turned on
Of the following, which best characterizes computers that use memory-mapped $I/O$? The computer provides special instructions for manipulating $I/O$ ports $I/O$ ports are placed at addresses on the bus and are accessed just like other memory locations To perform ... address register and call channel to perform the operation $I/O$ can be performed only when memory management hardware is turned on
asked Apr 22, 2018 in CO and Architecture Arjun 2k views
1 vote
1 answer
13
status Register & I/o
What is the work of status register in I/O operation ?
What is the work of status register in I/O operation ?
asked Aug 9, 2017 in CO and Architecture Sunil8860 383 views
2 votes
1 answer
14
MadeEasy Subject Test: CO & Architecture - Io Handling
The solution says that the answer should be 80, but applying the formula (x/y)*100, where x is 250 and y is 200 fraction comes out to be greater than 1. Am i making a mistake in interpreting x and y here?
The solution says that the answer should be 80, but applying the formula (x/y)*100, where x is 250 and y is 200 fraction comes out to be greater than 1. Am i making a mistake in interpreting x and y here?
asked Jul 8, 2017 in CO and Architecture kimaya 475 views
1 vote
2 answers
15
UGCNET-DEC2016-II: 38
Match the following w.r.t. Input/Output management: ... c-i; d-ii a-ii; b-i; c-iv; d-iii a-iv; b-i; c-ii; d-iii a-i; b-iii; c-iv; d-ii
Match the following w.r.t. Input/Output management: ... iii; b-iv; c-i; d-ii a-ii; b-i; c-iv; d-iii a-iv; b-i; c-ii; d-iii a-i; b-iii; c-iv; d-ii
asked Feb 11, 2017 in Operating System Debasmita Bhoumik 1.7k views
0 votes
4 answers
17
MadeEasy Subject Test: CO & Architecture - Io Handling
A device with data transfer rate of 8 KBps is connected to a CPU. Data is transferred bytewise. Let interrupt overhead be 2 μsec. The byte transfer time between the device interface register and CPU or memory is ... the device under interrupt mode over operating it under program-controlled mode is __________ . (Upto 1 decimal places)
A device with data transfer rate of 8 KBps is connected to a CPU. Data is transferred bytewise. Let interrupt overhead be 2 μsec. The byte transfer time between the device interface register and CPU or memory is negligible. The minimum performance gain of operating the device under interrupt mode over operating it under program-controlled mode is __________ . (Upto 1 decimal places)
asked Jan 26, 2017 in CO and Architecture Pankaj Joshi 1k views
19 votes
4 answers
20
GATE CSE 1990 | Question: 4-ii
State whether the following statements are TRUE or FALSE with reason: The data transfer between memory and I/O devices using programmed I/O is faster than interrupt-driven I/O.
State whether the following statements are TRUE or FALSE with reason: The data transfer between memory and I/O devices using programmed I/O is faster than interrupt-driven I/O.
asked Nov 24, 2016 in CO and Architecture makhdoom ghaya 3.6k views
2 votes
2 answers
21
GATE CSE 1987 | Question: 2b
State whether the following statements are TRUE or FALSE: Data transfer between a microprocessor and an I/O device is usually faster in memory-mapped-I/O scheme than in I/O-mapped -I/O scheme.
State whether the following statements are TRUE or FALSE: Data transfer between a microprocessor and an I/O device is usually faster in memory-mapped-I/O scheme than in I/O-mapped -I/O scheme.
asked Nov 9, 2016 in CO and Architecture makhdoom ghaya 648 views
4 votes
1 answer
22
GATE CSE 1987 | Question: 2a
State whether the following statements are TRUE or FALSE In a microprocessor-based system, if a bus (DMA) request and an interrupt request arrive sumultaneously, the microprocessor attends first to the bus request.
State whether the following statements are TRUE or FALSE In a microprocessor-based system, if a bus (DMA) request and an interrupt request arrive sumultaneously, the microprocessor attends first to the bus request.
asked Nov 9, 2016 in CO and Architecture makhdoom ghaya 1.2k views
0 votes
0 answers
23
Different types of ports and their difference
what is the difference between [1]Serial Port and Parallel Port, [2]Serial port in PC and Serial I/O interface
what is the difference between [1]Serial Port and Parallel Port, [2]Serial port in PC and Serial I/O interface
asked Nov 3, 2016 in CO and Architecture LavTheRawkstar 167 views
1 vote
0 answers
24
MadeEasy Workbook: CO & Architecture - I/O Handling
Q. A processor that communicates with remote terminals over telephone and other communication media in a serial fashion is called A) IO processor B) DMA controller C) Data communication processor D) USART Plz expalin each one???
Q. A processor that communicates with remote terminals over telephone and other communication media in a serial fashion is called A) IO processor B) DMA controller C) Data communication processor D) USART Plz expalin each one???
asked Oct 2, 2016 in CO and Architecture Hradesh patel 362 views
4 votes
1 answer
25
input-output
Consider a system employing interrupt-driven I/O for a particular device that transfers data at an average of 8 KB/s on a continuous basis. Assume that interrupt processing takes about 100 microsecond (i.e., the time to jump to the interrupt service routine (ISR), ... by this I/O device if it interrupts for every byte. Is it same as percentage of time CPU is in blocked state ?
Consider a system employing interrupt-driven I/O for a particular device that transfers data at an average of 8 KB/s on a continuous basis. Assume that interrupt processing takes about 100 microsecond (i.e., the time to jump to the interrupt service routine (ISR), execute it ... consumed by this I/O device if it interrupts for every byte. Is it same as percentage of time CPU is in blocked state ?
asked Sep 1, 2016 in CO and Architecture saurabh rai 3.7k views
3 votes
5 answers
26
ISRO2011-58
In DMA transfer scheme, the transfer scheme other than burst mode is cycle technique stealing technique cycle stealing technique cycle bypass technique
In DMA transfer scheme, the transfer scheme other than burst mode is cycle technique stealing technique cycle stealing technique cycle bypass technique
asked Jun 23, 2016 in CO and Architecture jothee 2.4k views
9 votes
4 answers
27
ISRO2011-39
Two control signals in microprocessor which are related to Direct Memory Access (DMA) are INTR & INTA RD & WR S0 & S1 HOLD & HLDA
Two control signals in microprocessor which are related to Direct Memory Access (DMA) are INTR & INTA RD & WR S0 & S1 HOLD & HLDA
asked Jun 22, 2016 in CO and Architecture jothee 3.9k views
6 votes
4 answers
28
ISRO2008-36
An interrupt in which the external device supplies its address as well as the interrupt requests is known as vectored interrupt maskable interrupt non maskable interrupt designated interrupt
An interrupt in which the external device supplies its address as well as the interrupt requests is known as vectored interrupt maskable interrupt non maskable interrupt designated interrupt
asked Jun 12, 2016 in CO and Architecture jothee 3.6k views
Page:
Dark theme
Muffin by Hélio Chun
Thanks to Q2A
...