Recent questions tagged io-handling

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1

I/O operation
Please Explain Every Point :) Ans. All are Correct

asked 4 days ago in CO & Architecture by Na462 Active (4.5k points) | 10 views

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2

Interrupt Driven I/O
Consider a system employing interrupt driven I/O for a particular device that transfer data at an average of 8 KB/sec on a continuous basis. Consider interrupt processing takes about 100 μsec i.e. time to jump to ISR, execute it and return to main program. The ... /O device if interrupts occur for every byte is ________. [Assume 1 K = 1024] (Upto 2 decimal places) Ans. 0.81

asked Jul 25 in CO & Architecture by Na462 Active (4.5k points) | 20 views

0 votes

1 answer

3

I/O Interface
State whether the following statement is TRUE or FALSE and why ? In a microprocessor-based system, if a bus (DMA) request and an interrupt request arrive simultaneously, the microprocessor attends first to the bus request.

asked May 4 in CO & Architecture by ankitgupta.1729 Loyal (6.6k points) | 89 views

+10 votes

4 answers

4

GATE1990-4-ii
State whether the following statements are TRUE or FALSE with reason: The data transfer between memory and $I/O$ devices using programmed $I/O$ is faster than interrupt-driven $I/O$.

asked Nov 24, 2016 in CO & Architecture by makhdoom ghaya Boss (40.1k points) | 840 views

+1 vote

1 answer

5

GATE1987-2b
State whether the following statements are TRUE or FALSE: Data transfer between a microprocessor and an $I/O$ device is usually faster in memory-mapped-$I/O$ scheme than in $I/O$-mapped -$I/O$ scheme.

asked Nov 9, 2016 in CO & Architecture by makhdoom ghaya Boss (40.1k points) | 245 views

+1 vote

2 answers

6

GATE1987-2a
State whether the following statements are TRUE or FALSE In a microprocessor-based system, if a bus (DMA) request and an interrupt request arrive sumultaneously, the microprocessor attends first to the bus request.

asked Nov 9, 2016 in CO & Architecture by makhdoom ghaya Boss (40.1k points) | 303 views

0 votes

0 answers

7

Different types of ports and their difference

asked Nov 3, 2016 in CO & Architecture by LavTheRawkstar Active (5.1k points) | 92 views

+2 votes

3 answers

8

ISRO2011-58
In DMA transfer scheme, the transfer scheme other than burst mode is cycle technique stealing technique cycle stealing technique cycle bypass technique

asked Jun 23, 2016 in CO & Architecture by jothee Veteran (99.8k points) | 1.8k views

+8 votes

3 answers

9

ISRO2011-39
Two control signals in microprocessor which are related to Direct Memory Access (DMA) are INTR & INTA RD & WR S0 & S1 HOLD & HLDA

asked Jun 22, 2016 in CO & Architecture by jothee Veteran (99.8k points) | 1.7k views

+5 votes

2 answers

10

ISRO2008-36
An interrupt in which the external device supplies its address as well as the interrupt requests is known as vectored interrupt maskable interrupt non maskable interrupt designated interrupt

asked Jun 12, 2016 in CO & Architecture by jothee Veteran (99.8k points) | 1.7k views

+3 votes

4 answers

11

ISRO-2013-52
Suppose we have variable logical records of lengths of $5$ bytes, $10$ bytes and $25$ bytes while the physical block size in disk is $15$ bytes. What is the maximum and minimum fragmentation seen in bytes? $25$ and $5$ $15$ and $5$ $15$ and $0$ $10$ and $5$

asked May 2, 2016 in Operating System by makhdoom ghaya Boss (40.1k points) | 2.7k views

0 votes

1 answer

12

Direct memory access is used for high-speed I/O devices.

asked Nov 18, 2015 in CO & Architecture by Anurag_s Loyal (8.1k points) | 478 views

0 votes

1 answer

13

bit rate of video terminal unit
what is bit rate of video terminal unit with 80 character/line , 8 bits/character and horizontal sweep time of 100 micro sec?

asked Oct 7, 2015 in Operating System by monali Junior (619 points) | 365 views

+5 votes

2 answers

14

ISRO2009-78
On receiving an interrupt from an I/O device,the CPU Halts for a predetermined time Branches off to the interrupt service routine after completion of the current instruction Branches off to the interrupt service routine immediately Hands over control of address bus and data bus to the interrupting device

asked Oct 5, 2015 in CO & Architecture by ajit Active (3.2k points) | 2.6k views

+12 votes

2 answers

15

GATE2004-IT-11, ISRO2011-33
What is the bit rate of a video terminal unit with $80$ characters/line, $8$ $\text{bits/character}$ and horizontal sweep time of $100$ $\text{µs}$ (including $20$ $\text{µs}$ of retrace time)? $8$ $\text{Mbps}$ $6.4$ $\text{Mbps}$ $0.8$ $\text{Mbps}$ $0.64$ $\text{Mbps}$

asked Nov 2, 2014 in Operating System by Ishrat Jahan Boss (19.1k points) | 2.3k views

+22 votes

2 answers

16

GATE2006-IT-8
Which of the following DMA transfer modes and interrupt handling mechanisms will enable the highest I/O band-width? Transparent DMA and Polling interrupts Cycle-stealing and Vectored interrupts Block transfer and Vectored interrupts Block transfer and Polling interrupts

asked Oct 31, 2014 in Operating System by Ishrat Jahan Boss (19.1k points) | 2.9k views

+16 votes

4 answers

17

GATE1996-25
A hard disk is connected to a $50$ MHz processor through a DMA controller. Assume that the initial set-up of a DMA transfer takes $1000$ clock cycles for the processor, and assume that the handling of the interrupt at DMA completion requires $500$ clock cycles for the processor. The ... 0.98 16 Kbytes 0.90 16 Kbytes 0.99 64 Kbytes 0.95 64 Kbytes 0.995 Size Hit Ratio 250 M bytes 1.0

asked Oct 10, 2014 in CO & Architecture by Kathleen Veteran (59.5k points) | 2.2k views

+8 votes

1 answer

18

GATE1996-1.24
For the daisy chain scheme of connecting I/O devices, which of the following statements is true? It gives non-uniform priority to various devices It gives uniform priority to all devices It is only useful for connecting slow devices to a processor device It requires a separate interrupt pin on the processor for each device

asked Oct 9, 2014 in CO & Architecture by Kathleen Veteran (59.5k points) | 1.3k views

+16 votes

2 answers

19

GATE1996-1.20, ISRO2008-56
Which of the following is an example of spooled device? A line printer used to print the output of a number of jobs A terminal used to enter input data to a running program A secondary storage device in a virtual memory system A graphic display device

asked Oct 9, 2014 in Operating System by Kathleen Veteran (59.5k points) | 2.5k views

+3 votes

1 answer

20

GATE1995-17
An asynchronous serial communication controller that uses a start-stop scheme for controlling the serial I/O of a system is programmed for a string of length seven bits, one parity bit (odd parity) and one step bit. The transmission rate is $1200$ bits/second. What ... What is the size of the video buffer RAM for the display to be used in monochrome ($1$ bit per pixel) graphics mode?

asked Oct 8, 2014 in Operating System by Kathleen Veteran (59.5k points) | 494 views

+8 votes

3 answers

21

GATE1997-2.4
The correct matching for the following pairs is: (A) DMA I/O (1) High speed RAM (B) Cache (2) Disk (C) Interrupt I/O (3) Printer (D) Condition Code Register (4) ALU A-4 B-3 C-1 D-2 A-2 B-1 C-3 D-4 A-4 B-3 C-2 D-1 A-2 B-3 C-4 D-1

asked Sep 29, 2014 in CO & Architecture by Kathleen Veteran (59.5k points) | 779 views

+11 votes

3 answers

22

GATE1998-1.29
Which of the following is an example of a spooled device? The terminal used to enter the input data for the C program being executed An output device used to print the output of a number of jobs The secondary memory device in a virtual storage system The swapping area on a disk used by the swapper

asked Sep 26, 2014 in Operating System by Kathleen Veteran (59.5k points) | 952 views

+16 votes

2 answers

23

GATE2005-20
Normally user programs are prevented from handling I/O directly by I/O instructions in them. For CPUs having explicit I/O instructions, such I/O protection is ensured by having the I/O instruction privileged. In a CPU with memory mapped I/O, there is ... s) I/O protection is ensured by a hardware trap I/O protection is ensured during system configuration I/O protection is not possible

asked Sep 22, 2014 in Operating System by Kathleen Veteran (59.5k points) | 2.2k views

+19 votes

6 answers

24

GATE2005-19
Which one of the following is true for a CPU having a single interrupt request line and a single interrupt grant line? Neither vectored interrupt nor multiple interrupting devices are possible Vectored interrupts are not possible but ... interrupts and multiple interrupting devices are both possible Vectored interrupts are possible but multiple interrupting devices are not possible

asked Sep 22, 2014 in Operating System by Kathleen Veteran (59.5k points) | 3.2k views

+18 votes

3 answers

25

GATE2008-64, ISRO2009-13
Which of the following statements about synchronous and asynchronous I/O is NOT true? An ISR is invoked on completion of I/O in synchronous I/O but not in asynchronous I/O In both synchronous and asynchronous I/O, an ISR (Interrupt Service Routine) is ... the process waiting for the completion of I/O is woken up by the ISR that is invoked after the completion of I/O

asked Sep 12, 2014 in CO & Architecture by Kathleen Veteran (59.5k points) | 4.1k views

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