When a non-maskable interrupt occurs, the cpu finishes its current instructions and then jumps to a hardcoded ISR. This is a common ISR to all interrupts. It contains a sequence of instructions which poll each device sequentially (according to their priority level).
The cpu executes these instructions by placing the address of the appropriate IO module along with proper register select (RS) bits to select the status register and check whether that particular device has caused the interrupt or not. If not, the cpu places the address of the next sequential io module. If yes, the cpu jumps to the respective ISR.
Answer should Be B