Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 17

Question

Consider a pipelined system with these $4$ phases:

FI –  Fetch instruction
DA – Decode and calculate address
FO – Fetch Operand
EX-  Execute instruction

Each phase requires one clock cycle. There were four instructions in the following program:

$\begin{array}{|l|l|}  \hline \text{Load } R1 & \leftarrow M[312] \\ \hline \text{ADD } R2 & \leftarrow R1 + M[313] \\ \hline \text{INC } R3 & \leftarrow R2+1 \\ \hline \text{Store } M[314] & \leftarrow R3 \\ \hline \end{array}$

If there exists pipeline hazards , then the number of clock cycles required to complete the above program  is _________

Answer 1

Clocks   1     2      3       4     5        6       7       8       9       10

Load     FI   DA    FO    EX

ADD           FI      DA   ----    FO     EX

INC                     FI     ----    DA     ----    FO     EX

Store                           ----    FI      -----   DA     ----      FO      EX

Total 10 clock cycles are required to complete those instructions.

Comments

@ bikram sir .. thanx  sir

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Why we can't do DA stage of I3 instruction in the 4th cycle itself.

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Even I have the same doubt @Rajnish Kumar 1. Can someone tell me why we can't dod DA stage of I3 instruction in  4th cycle. Same thing seemed to be have done to I4 instruction too. But why?