in a virtual memory system which of the following is not possible
a)TLB miss with no page fault
b)TLB miss with page fault
c)TLB hit and page fault
d) none
the answer given is option d
but.........TLB is a memory that stores a part of the pagetable....and if its a hit , then it directly goes to the process and need not refer the pagetable right?
option a) TLB is checked, its a miss and the pagetable is checked and its present there , therefore no page fault ------->this is posssible
option b)TLB is checked, its a miss and the pagetable is checked and its not present there , therefore page fault ------->this is posssible
option c)TLB is checked, its a hit...when its a hit, the pagetable is not checked itself....how can u consider a pagefault there??
may be there is something wrong in the concept that i have understood
please help