nice set of questions..🖐🏻🖐🏻👍🏻
@saxena0612
1) after HALT instruction the next address is in PC
2) while calculating effective memory access time IF NOTHING IS GIVEN use hierarchical only, But if its said Write Through cache and read write all operations are involved use simultaneous access while WRITING only..
3) no; like if in 1 sec 8 bits are transferred where 3 bits are fir synchronization purpose between sender and receiver then DTR is 5 bps
4) 9 States in counter , 3 are similar;;;;; so 7 states are distinct for which 3 ff's are needed at least, then to distinguish 3 similar states we need 2 ff's at least so IN TOTAL 5 FF'S ARE NEEDED
EG+++++>>>>
1,2,0,3,4,0,5,6,0 then repeat..
for 1,2,3,4,5,6,0 we need 3 ff's ; and for three 0's we need 2 ff's...in total 5
5) Yes ,like in worst case of Quick Sort. Space = 0(n) as stack depth is n which is recursion depth
6) total number of subnets=don't exclude anything. total number of useful subnets=exclude 2
7) no "minimum" no optimisation
8) first cache as TLB is generally physically tagged and cache is virtually...so you have to get the physical address first.But physically addressed cache are present also
refer: https://gateoverflow.in/31112/which-is-accessed-frist-tlb-or-cache
@Arjun@Bikram **please check Thanks**