I got answer 450 but the answer given is 410
400(to access 4 words in L2) + 40(4 access to store word read from L2 in L1) + 10(final one access by CPU) = 450
Consider the 2 level memory Hierarchy given below. Block size in $1^{\text {st }}$ level memory is 4 words and Block size in $2^{\text {nd }}$ level memory is 32 words $1^{\text {st }}$ level memory has 4 blocks.
$1^{\text {st }}$ level access time is $10 \mathrm{~ns} /$ word but $2^{\text {nd }}$ level memory access time is $100 \mathrm{~ns} /$ word. When there is a miss in $1^{\text {st }}$ level memory and a hit in $2^{\text {nd }}$ level memory, a block is transferred from $2^{\text {nd }}$ level to $1^{\text {st }}$ level memory and then a word is transferred to CPU. Time taken for this transfer (in n.s) is $\qquad$ .
