4 votes 4 votes CO and Architecture cache-memory effective-memory-access gateforum-test-series + – Sumaiya23 asked Jan 20, 2018 Sumaiya23 596 views answer comment Share Follow See all 8 Comments See all 8 8 Comments reply Show 5 previous comments vishal chugh commented Jan 20, 2018 reply Follow Share What is wrong with @Sumaiya23 solution can you please tell. 0 votes 0 votes Higgs commented Jan 20, 2018 reply Follow Share @vishal 100 memory references. | | \|/ _____________ | L1 Cache | //84 hits in L1 cache itself. |_____________| Remaining 16 references | | \|/ ____________ | L2 Cache | //Given, Out of 16 references made to L2, 8 hits in L2 cache i.e. 8 misses. |____________| //Therefore, hit ratio = miss ratio = 0.5 for L2 cache. Remaining 8 references | | \|/ ________________ | Main Memory | |_______________ | Therefore, Avg time = 0.84*1 + 0.16*0.5*(5+1) + 0.16*0.5*(1+5+50) 3 votes 3 votes vishal chugh commented Jan 21, 2018 reply Follow Share Thanks again for this answer :) 1 votes 1 votes Please log in or register to add a comment.
0 votes 0 votes correct answer will be = 5.8 Average memory access time=1+(16/100)*(5+(8/16)*50)=5.8 Average memory access time=hit time of L1+miss rate of L1*(hit time of L2+miss rate of L2*miss penalty of L2 to memory) Gyan Ranjan answered Jul 22, 2020 Gyan Ranjan comment Share Follow See all 0 reply Please log in or register to add a comment.