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A computer has a $256\text{-KByte}$, 4-way set associative, write back data cache with block size of $32\text{-Bytes}$. The processor sends $32\text{-bit}$ addresses to the cache controller. Each cache tag directory entry contains, in addition to address tag, $2$ valid bits, $1$ modified bit and $1$ replacement bit.

The number of bits in the tag field of an address is

  1. $11$
  2. $14$
  3. $16$
  4. $27$

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Best answer
52 52 votes
Total cache size $= 256\ KB$
Cache block size $=32\text{ Bytes}$
So, number of cache entries $=\dfrac{ 256\ K}{32}=8\ K$

Number of sets in cache $=\dfrac{ 8\ K}{4}=2\ K$ as cache is $4\text{-way}$ associative.

So, $\log(2048) = 11\ \text{bits}$ are needed for accessing a set. Inside a set we need to identify the cache entry.

No. of memory block possible $=\dfrac{\text{Memory size}}{\text{Cache block size}}$

$=\dfrac{2^{32}}{32} = 2^{27}$.

So, no. of memory block that can go to a single cache set

$=\dfrac{2^{27}}{2^{11}}$

$=2^{16}.$

So, we need $16\text{ tag bits}$ along with each cache entry to identify which of the possible $2^{16}$ blocks is being mapped there.

Correct Answer: $C$
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.......……………………………......................…....….

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Each cache tag directory entry contains, in addition to address tag,  2 valid bits, 1 modified bit and 1 replacement bit.

so this info is irrelevant I guess

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