13 13 votes Many microprocessors have a specified lower limit on clock frequency (apart from the maximum clock frequency limit) because ? CO & Architecture co-and-architecture clock-frequency + – srinath 2.9k views answer comment Share Follow Print 0 reply Please log in or register to add a comment.
Best answer 24 24 votes Clcok frequency becomes low means time period of clock becomes high. When this time period increses beyond the time period in which the non-volatile memory contents must be refreshed, we loose those contents. So, clock frequence can't go below this value. The cache, register etc. inside CPU and RAM for primary memory are all examples of volatile memory and needs refresh within the specified time period or else will loose their contents. Non-volatile memory are being developed and computers in future should be tailor made for that. Arjun answered Sep 3, 2014 • selected Oct 10, 2017 by srestha Arjun comment Share Follow See all 5 Comments 5 5 Comments reply shikhar_deep05 commented Nov 15, 2016 reply Follow flag @Arjun Why you said cache, register and RAM comes under non volatile memory? 2 2 replyShare Arjun commented Nov 15, 2016 reply Follow flag Sorry, it was a typo. Thanks.. 0 0 replyShare Hemant Parihar commented Dec 28, 2017 reply Follow flag non-volatile memory contents must be refreshed. I think it should also be volatile. 12 12 replyShare txds commented Nov 23, 2019 reply Follow flag do contents get lost in volatile memory even if there's no power failure? 2 2 replyShare rohith1001 commented Dec 22, 2019 reply Follow flag Yes. RAM has to be refreshed periodically. Source: Wiki Memory refresh is the process of periodically reading information from an area of computer memory and immediately rewriting the read information to the same area without modification, for the purpose of preserving the information.[1] In a DRAM chip, each bit of memory data is stored as the presence or absence of an electric charge on a small capacitor on the chip.[2][3] As time passes, the charges in the memory cells leak away, so without being refreshed the stored data would eventually be lost. For example, the current generation of chips (DDR SDRAM) has a refresh time of 64 ms and 8,192 rows, so the refresh cycle interval is 7.8 μs.[5][9] 7 7 replyShare Please log in or register to add a comment.