GATE CSE 2019 | Question: 45

Question

A certain processor deploys a single-level cache. The cache block size is $8$ words and the word size is $4$ bytes. The memory system uses a $60$-MHz clock. To service a cache miss, the memory controller first takes $1$ cycle to accept the starting address of the block, it then takes $3$ cycles to fetch all the eight words of the block, and finally transmits the words of the requested block at the rate of $1$ word per cycle. The maximum bandwidth for the memory system when the program running on the processor issues a series of read operations is  ______$\times 10^6$ bytes/sec.

Comments

what is happening physically here 

==> The processor asks for data (here we have to note that every read is a cache miss, so the memory system is continuously busy fetching whole blocks.).

==> The memory controller spends 1 cycle to know which 32-byte block you want.

==> The actual DRAM chips take 3 cycles to find that chunk of data internally.

==> Finally, the memory controller send out the data to the cache, 1 word which is 4bytes per cycle, taking 8 cycles.

==> Total time = 12 cycles. At 60 MHz, 12 cycles = 0.2 microseconds .

==> Since you transfer 32 bytes every 200 ns, in 1 second you transfer \( 32 / (200 \times 10^{-9}) = 160 \times 10^6 \) bytes. This is the maximum bandwidth.

 

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For Visual understanding must visit @HitechGa answer  https://gateoverflow.in/302803/gate-cse-2019-question-45?show=363443#a363443

 

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total cycle = 1 + 3+ 8 = 12

block size = 8 words = 32 byte

 first cycle for fetch  and 3 cycle to take fatch all 8 block and for transmit 3 more cycle

So ,  mem badwidth = 32/12 cycle time

                                  32*60*10^6 / 12 = 160*10^

final answet = 160 byte / sec

Answer 1

Time to transfer a cache block $ = 1+3+8 = 12$ cycles.

i.e., $4$ bytes $\times 8 = 32$ bytes in $12$ cycles.

So, memory bandwidth $ = \frac{32}{12 \text{ cycle time}} =\frac{32}{12/(60 \times 10^6)}= 160 \times 10^6 $ bytes/s

Comments

question says " maximum bandwidth for the memory system when the program running on the processor issues a series of read operations ". So in case of maximum bandwidth, shouldn't we consider a case of no miss in cache. In that case, i word that is 4 bytes will be transferred in 1 clock cycle. Therefore BW should be 240 in that case. Please correct me.

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But we can't get rid of the first miss right? The first reference miss will be there at any cost.  Except for this miss, we got to take care that we don’t face any other miss.

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Yes, there is exact matching with that lecture.

Answer 2

$\underline{\mathbf{Answer:}}\;\bbox[lightgreen, 5px, border: 2px solid black]{\color {black} {160 \times 10^6\; \frac{\mathrm {Bytes}}{\mathrm{sec}}}}$

$\underline{\mathbf{Explanation:}}$

$\text {Given frequency} = 60\ \text{MHz}$

This means that the processor completes $\color{green}{60\times 10^6 \;\text{cycles in}\;1 \;\text{second}}.$

$\therefore $ One cycle is completed in $\dfrac{1}{60\times 10^6 }\; \text{seconds}\;\;\text{[Using Unitary Method]}$

Now, To service a cache miss, number of cycles needed $$ \color{blue}{= 1\;\text{cycle}}\;\color{blue}{\text{(to accept starting address of the block)}} + 3\;\text{cylces}\;\color{blue}{\text{(to fetch all the $8$ words of the blocks)}}$$

$$+  \underbrace{8\times1}_\text{$\because$1 word per cycle}\;\text{cycles}\;\color{blue}{\text{(to transmit all $8$ words of the block)}}=  12  \;\text{cycles}$$

$\underline{\color{red}{\mathbf{Note:}}}$ Total data is the data which is used for trasmitting the words of the requested block at the rate of $\mathbf{1}$ word per cycle $=\mathbf{8\;words \times 4\;Byte\;(Size\; of\; each\; word)}$

$ \begin{align}\therefore \mathbf{Bandwidth} \require{cancel} &= \dfrac{\text{Total Data}}{12 \;\text{cycle time}} \\&= \dfrac{8\times4\;\text{Bytes}}{12\;\text{cycles }\times1\; \text{cycle time}} \\&= \dfrac{32}{12 \times \dfrac{1}{60\times10^6}} \\&= \require{cancel} \dfrac{32\times \cancel {60}^{5} \times 10^6}{\cancel{12}^1}\\& = 5 \times 32 \times {10}^6 \\&= \color {black}{160 \times 10^6 \; \dfrac{\text{Bytes}}{\mathrm{sec}}}\end{align}$

$\therefore  \bbox[lightgreen, 5px, border: 2px solid black]{\color {black}{160 \times 10^6 \; \dfrac{\text{Bytes}}{\mathrm{sec}}}}$ is the correct answer.

Comments

Great!

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Nice👍

Answer 3

Few things which are to be noted here are as follows. The memory controller is a part of the “memory system”. The memory system quite obviously also has the memory chip where the data are actually stored. Now the question asks to find the maximum bandwidth of the “memory system”. Now bandwidth of the memory system is the data transfer speed of the memory system, i.e. considering memory system as a black box, how much data can be retrieved from it per unit time.

Now as per the question it takes $1$ cycle to select the first address of the block by the memory controller.

It takes $3$ cycles to read $8$ words from the memory chip to the memory controller. [Note that the memory controller is a part of the memory system, so $8/3$ words/cycle is not the required bandwidth, we need to find data rate for data entering or leaving the memory system!!]

Lastly it takes $8$ cycles to transfer the $8$ words to the data bus.

So in a period of $1+3+8(=12)$ cycles, $8$ words or $32$ bytes of data are retrieved from the memory system. So in a system which issues a series of read request, the maximum bandwidth of the memory system shall occur when there is a miss!! [Had there been no miss, the memory system shall be idle and bandwidth shall be $0$ in that case.] So in a system issuing a series of read requests, in $12$ cycles or $12*\frac{1}{60 *10^6}$ secs we can get max of $32$ bytes of data out of the memory system.

So required bandwidth = $\frac{32}{12*\frac{1}{60 *10^6}}$ bytes/sec = $160 * 10^6$ bytes/sec

Comments

Just one crucial point here that i seem is important by @HitechGa is [Had there been no miss, the memory system shall be idle and bandwidth shall be 0 in that case.]

agr koi miss hi nhi hoga to bandwidth 0 hogi kuki koi byte transfer hi nhi hoga from memory system to cache.(if there isn't any miss then no byte will be transferred which will lead to bandwidth as 0.)

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The transfer written here is done from the memory controller to cache right ? or is from cache to user ??

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The bandwidth would not be 0 i think in 100% hits at cache; because  thats the throughput. Bandwidth is like a intrinsic property ; So i think max bandwidth would mean the value in ideal / non-conditional cases.

But not sure

Answer 4

$Cache\ block = 8\ words$

$Word\ size = 4\ bytes$

$Cache\ block\ size = 32\ bytes$

$frequency = 60\ MHz$

$Cycle\ time(\#\ of seconds/cycle) = \dfrac{1}{frequency} = \dfrac{1}{60×10^6} seconds$

$Cache\ miss\ time:$

$1\ cycle(Address\ of\ the\ block)$

$3\ cycles (fetch\ all\ the\ 8-words\ of\ the\ block)$

$8\ cycles (transfer\ of\ 8-words\ at\ the\ rate\ of\ 1\ cycle/word )$

$Total = 12\ cycles$

$Total\ time= \dfrac{12}{60×10^6}sec$

$Total\ bandwidth = \dfrac{total\ data}{total\ time} = \dfrac{32\ bytes}{\dfrac{12}{60×10^6}} = 160 × 10^6 bytes/second$

$Answer: 160$

Comments

Good answer.

Just edit it little more.

From bottom $3^{rd}$ lin is $10^6$

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Done editing.

Thank you.

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जबरदस्त।🛡️🤩

Answer 5

My approach:

Total cycles = 1+3+8 =12

This way I got it as 160 bps

Plzx confirm :0

Comments

since it is written series of read operation I assume(prohibited in gate exam) that program is of video application hence data would be distinct so every time after 12 cycle there would be miss . Just hope for the best

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Yeah , according to this  answer should be 240 since cpi =8 ( 1word)

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It is given series of read operations, so i think cpi would be 8 cycles since pipelining is used, so answer should be 240

Answer 6

total number of cycles = 1 + 3 + 8 = 12

total data transferred = 8 words * 4 bytes per word = 32 bytes

frequency of clock = 60 MHz

so bandwidth = total data transferred/total time taken

 = 32  bytes/(12cycles/(60*10^6cycles per sec))

= 160 * 10 ^ 6 bytes/sec

It is maximum in the case when every read request is a cache miss.