edited by
1,205 views

2 Answers

5 votes
5 votes
For n bit cla ,the no of AND gate is n*(n+1)/2

So,for 5 bit, the no of AND gate is 15
0 votes
0 votes

We know the equation carry look ahead generator circuit is

$c_{i}=g_{i-1}+c_{i-1}.p_{i-1}$

$c_{1}=g_{0}+c_{0}.p_{0}$

$c_{2}=g_{1}+c_{1}.p_{1}$

$\Rightarrow c_{2}=g_{1}+\left ( g_{0}+c_{0}.p_{0}\right )p_{1}$

$\Rightarrow c_{2}=g_{1}+g_{0}.p_{1}+c_{0}.p_{0} .p_{1}$

$c_{3}=g_{2}+c_{2}.p_{2}$

$\Rightarrow c_{3}=g_{2}+\left (g_{1}+g_{0}.p_{1}+c_{0}.p_{0} .p_{1}\right )p_{2}$

$\Rightarrow c_{3}=g_{2}+g_{1}.p_{2}+g_{0}.p_{1}.p_{2}+c_{0}.p_{0} .p_{1}.p_{2}$

$c_{4}=g_{3}+c_{3}.p_{3}$

$\Rightarrow c_{4}=g_{3}+\left (g_{2}+g_{1}.p_{2}+g_{0}.p_{1}.p_{2}+c_{0}.p_{0} .p_{1}.p_{2}\right )p_{3}$

$\Rightarrow c_{4}=g_{3}+g_{2}.p_{3}+g_{1}.p_{2}.p_{3}+g_{0}.p_{1}.p_{2}.p_{3}+c_{0}.p_{0} .p_{1}.p_{2}p_{3}$

$c_{5}=g_{4}+c_{4}.p_{4}$

$\Rightarrow c_{5}=g_{4}+\left (g_{3}+g_{2}.p_{3}+g_{1}.p_{2}.p_{3}+g_{0}.p_{1}.p_{2}.p_{3}+c_{0}.p_{0} .p_{1}.p_{2}p_{3}\right )p_{4}$

$\Rightarrow c_{5}=g_{4}+g_{3}.p_{4}+g_{2}.p_{3}.p_{4}+g_{1}.p_{2}.p_{3}.p_{4}+g_{0}.p_{1}.p_{2}.p_{3}.p_{4}+c_{0}.p_{0} .p_{1}.p_{2}p_{3}p_{4}$

Total 15 AND gates.

if total AND gates were asked in whole carry-look ahead adder, than it would be n*(n+1)/2 + n.

But here it is asking, The number of AND gates are present inside a 5-bit carry look ahead generator circuit are $15$

edited by

Related questions

1 votes
1 votes
2 answers
3
Puja Mishra asked Dec 18, 2017
735 views
can anyone tell me wat is the right equation for carry generator in carry lookahead adder ?? Confused ..$ C_{i} = G_{i}+P_{i}C_{i-1}$$ C_{i+1}=G_{}i+P_{}iC_{}i$
0 votes
0 votes
0 answers
4
junaid ahmad asked Dec 8, 2017
723 views
Q.A one bit full adder takes 75 nsec to produce sum and 50 nsec to produce carry.A 4 bit parallel adder is designed using this type of full adder. The maximum rate of add...