1 votes 1 votes Consider a hypothetical processor which supports expand opcode technique. A 32 bit instruction is place in 256MW memory. If there exist 10, one address instruction then how many zero-address instruction are possible. CO and Architecture co-and-architecture pipelining control-unit ieee-representation + – iabhay.gupta asked Dec 11, 2022 iabhay.gupta 678 views answer comment Share Follow See all 0 reply Please log in or register to add a comment.
2 votes 2 votes Instruction size = $32$ $bit$ Address size = $\log 2^{28}$ = $28$ $bit$ Total number of zero address instruction = $2^{32}$ – $10*2^{28}$ = $2^{28}(2^{4} - 10)$ = $6*2^{28}$ Shubhodeep answered Dec 11, 2022 Shubhodeep comment Share Follow See all 0 reply Please log in or register to add a comment.