Ace Test Series | Computer Organistaion

Question

A pipelined processor with a separate instruction & data cache has 5- stages, the cycle time 30 nano sec. It can start a new instruction on every cycle when there were no hazards. It is used with copy- back data cache with a block size of one - word. T cache = 30 ns, Tm = 80 ns. The hit ratio of cache 90%. ignore write back time of dirty pages. If 25% of all instructions are load and store which only result hazards. What is the throughout of CPU.

a) 31 MIPS
b) 24 MIPS
c) 48 MIPS
d) 10 MIPS

Comments

What is the answer to this one? It seems like a great question. I banged my head for 1 hour and don’t know whether what I did was right or not. Please post the answer, if you already solved or if there is a answer key.
Thankyou.

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There were few edits in the question which I have updated now.
The given answer key is option A.
I am getting the efficiency which is coming out to be 38.7755%.
But, I’m not getting the throughput. Like how to do it?

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@Sachin Mittal 1 sir, @Arjun sir, @Deepak Poonia sir can please look into this question.
How to proceed with such kind of questions

Answer 1

Option A) is correct

It is given that the pipelined processor has separate instructions and data cache. So for instructions it will use instructions cache and for data it will use data cache.
We know that Throughput =number of instructions/total execution time.

Given,
It can start new execution on every cycle when there is no hazard,i.e CPI=1
Cycle time=30ns (for instructions)

Now for data cache
Tcache=30ns
Tm=80ns
Hit%=90%
avg access time =hit(Tcache) +(1-hit) {Tcache+Tm}

                              =0.9(30) +0.1(30+80) ns

                             =27+11=38ns

 
And given that total 25% of all instructions are load and store (uses data cache) other 75% uses instruction cache.

 
So avg time =25% of Access time in data cache + 75% of access time in instructions cache

=(0.25*38+0.75*30)ns

=32ns

 
There are 3 types of Hazard =Data hazard, Control hazard and Structural hazard.

Data hazards occurred in execution time, so in this case no data hazard

Control hazard occurred mainly in brunch instructions but there is no case of brunch instructions.

Structural hazard occurred due to resource conflict. It is mentioned also in the question,that hazard occurred only in store and load.

******But we know that structural hazard can be resolve using Register Renaming. According to register renaming we divide the memory in two part i) Code or Instructions memory ii) Data memory

That's what actually done in our case to resolve the hazard. In the question it is mentioned that it uses separate memory for instructions and data, so technically no hazard occurs.

But due to separate memory avg time cycle changes in our case it is 32 ns.

There is no change in CPI which remains 1.

So avg execution time for one instruction(ET) =CPI*Time cycle

=1*32 ns

=32x10^-9 sec

And now Throughput =total instructions/total execution time 

=1/ET

=1/32x10^-9 sec

=0.03125 x10^9 instructions/sec

=31.125 x10^6 instructions/sec

= 31MIPS (answer).