ISRO CSE 2008 | Question: 45

Question

The TRAP is one of the interrupts available in $\textsf{INTEL 8085}.$ Which one of the following statements is true of TRAP ?

• A. it is level triggered
• B. it is negative edge triggered
• C. it is $\textsf{+ve}$ edge triggered
• D. it is both $\textsf{+ve}$ and $\textsf{-ve}$ edges triggered

Comments

Please explain why it has to be both positive and negative edge triggered.

I have found that it should be both edge and level triggered.

Refer: https://electronics.stackexchange.com/questions/21886/what-does-edge-triggered-and-level-triggered-mean

Answer 1

Answer is D

it is both +ve and -ve edges triggered

https://www.scribd.com/doc/56447278/Microprocessor-Multiple-Choice-Ques

http://www.karunya.edu/cse/downloads/COMPUTER%20ARCHITECURE.ppt

Answer 2

it is +ve edge triggered

TRAP must go high and remain high until it is acknowledged.

Comments

Answer is D it is both +ve and -ve edges triggered

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D is correct

Answer 3

$\underline{\textbf{Answer}\Rightarrow}$ None is the correct answer here.

Option $\mathbf{(D)}$ should be both edge as well as level triggered.

$\underline{\textbf{Answer}\Rightarrow}$

$\mathbf{8085}$ has $\mathbf 3$ $\color{blue}{\text{maskable}}$ vectored interrupts $\textbf{(RST 7.5, RST 6.5 and RST 5.5)}$, $\color{magenta}{\text{one non-maskable}}$ interrupt (TRAP), and $\color{green}{\text{one externally serviced interrupt (INTR)}}$.

$\mathbf{RST\; 5.5}$ interrupt is edge triggered (latched)

$\mathbf{RST\; 5.5}$ and $\mathbf{6.5}$ are level sensitive.

$\mathbf{TRAP}$ Both edge as well as level triggered to avoid false interrupt.

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https://en.wikipedia.org/wiki/Intel_8085

https://electronics.stackexchange.com/questions/21886/what-does-edge-triggered-and-level-triggered-mean

Answer 4

The TRAP interrupt is edge and level sensitive. Hence, to initiate TRAP, the interrupt signal has to make a low to high transition and then it has to remain high until the interrupt is recognized.