UGC NET CSE | December 2023 | Part 2 | Question: 15

Question

A system bus in which each data item is transferred during a time slice known in advance to both units source and destination is called:

• A. MIMD
• B. DMA
• C. asynchronous bus
• D. synchronous bus

Answer 1

• Synchronous Bus →
  Data transfer fixed, pre-defined time slice (clock cycle) me hota hai
  ✔️ Source ko bhi timing pata hoti hai
  ✔️ Destination ko bhi timing pata hoti hai

• Asynchronous Bus ❌ → timing fixed nahi hoti

• DMA ❌ → data transfer technique hai, bus type nahi

• MIMD ❌ → processor architecture hai

👉 answer = Synchronous Bus ✅