Register

GO Classes DPP | COA |CACHE MEMORY

593 views
4 4 votes

Consider a $2$-way set associative cache (initially empty) with a total of 16 cache blocks. The main memory consists of 256 blocks and the requests for memory blocks are in the following order:
$$0,255,1,4,3,8,133,159,216,129,63,8,48,32,73,92,155$$
Which one of the following memory blocks WILL be in the cache if an LRU replacement policy is used?

  1. $0$
     
  2. $8$
     
  3. $129$
     
  4. $216$

3 Answers

0 0 votes

8 Sets (16 blocks / 2-way). Set Index: Block % 8.

Trace (Set Index: [MRU, LRU]):

  • Set 0: 0 → [0]

  • Set 7: 255 → [255]

  • Set 1: 1 → [1]

  • Set 4: 4 → [4]

  • Set 3: 3 → [3]

  • Set 0: 8 → [8, 0]

  • Set 5: 133 → [133]

  • Set 7: 159 → [159, 255]

  • Set 0: 216 (Evict 0) → [216, 8]

  • Set 1: 129 (Evict 1) → [129, 1]

  • Set 7: 63 (Evict 255) → [63, 159]

  • Set 0: 8 (Hit) → [8, 216]

  • Set 0: 48 (Evict 216) → [48, 8]

  • Set 0: 32 (Evict 8) → [32, 48]

  • Set 1: 73 (Evict 1) → [73, 129]

  • Set 4: 92 (Evict 4) → [92, 4]

  • Set 3: 155 (Evict 3) → [155, 3]

Final State: Options (0, 8, 216) evicted. 129 remains in Set 1.

Answer: (C) 129

0 0 votes

S= 8 (S0 to S7); CL= 16 (CL0 to CL15)

 

Available Slots in the Memory-

 

S0- MB48, MB32

S1- MB01, MB129

S2- /

S3- MB03, MB155

S4- MB04, MB192

S5- MB133

S6- /

S8- MB63, MB159

 

(MB)mod.S

 

Answer- MB129

Voting & Accepting an answer helps improve the community
Answer:
← Previous · M/c instructionNext → · GO Classes DPP | COA...
← Previous in category · M/c instructionNext in category → · GO Classes DPP | COA...
Position:
Show:

Related questions

8 8 votes
4 4 answers
698
698 views
GO Classes asked Sep 27, 2025
698 views
GO Classes DPP | COA |CACHE MEMORY
An $8$-way set-associative cache memory unit with a capacity of $64$ KB is built using a block size of $16$ words. The word length is $32$ bits. The size of the physical ...
6 6 votes
1 1 answer
513
513 views
GO Classes asked Sep 27, 2025
513 views
GO Classes DPP | COA |CACHE MEMORY
A computer system has an L1 cache, an L2 cache, and a main memory unit. The block size in L2 cache is 16 words. The data bus between the L2 cache and main memory is 4 wor...
11 11 votes
6 6 answers
1.7k
1.7k views
GO Classes asked Sep 27, 2025
1,699 views
GO Classes DPP | COA |INSTRUCTION FORMAT
In a $12$ -bit computer instruction format, the size of the address field is $3$ bits. The computer uses an expanding OP code technique and has $12$ two-address instructi...
3 3 votes
1 1 answer
652
652 views
GO Classes asked Sep 27, 2025
652 views
GO Classes DPP | COA |SPEEDUP
The baseline execution time of a program on a single-core machine is $200$ nanoseconds (ns). The code corresponding to $90\%$ of the execution time can be fully paralleli...