Recent questions tagged goclasses-coa-practice-questions

In a $12$ -bit computer instruction format, the size of the address field is $3$ bits. The computer uses an expanding OP code technique and has $12$ two-address instructi...

The baseline execution time of a program on a single-core machine is $200$ nanoseconds (ns). The code corresponding to $90\%$ of the execution time can be fully paralleli...

An $8$-way set-associative cache memory unit with a capacity of $64$ KB is built using a block size of $16$ words. The word length is $32$ bits. The size of the physical ...

A computer system has an L1 cache, an L2 cache, and a main memory unit. The block size in L2 cache is 16 words. The data bus between the L2 cache and main memory is 4 wor...

Consider a $2$-way set associative cache (initially empty) with a total of 16 cache blocks. The main memory consists of 256 blocks and the requests for memory blocks are ...

A DMA controller transfers data from an I/O device to main memory using cycle stealing. The CPU is running at a frequency of $50$ MHz . The I/O device transfers data at a...

An instruction set architecture is implemented using two different processor designs: P1: A single-cycle processor with a clock period of $10 \ \text{ns}$ .P2: A multi-cy...

In a system where multiple I/O devices are connected using a daisy-chaining scheme for interrupt handling, three devices, D1, D2, and D3 are connected in that order of pr...

A processor uses 16-bit instructions and has a byte-addressable memory. It has a post-increment register indirect addressing mode, $\mathrm{(Rx)+}$, which first fetches t...

A processor has a $5$-stage instruction pipeline: Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Register Writeback (WB). The clo...

A computer's main memory unit has a peak theoretical bandwidth of $12.8 \mathrm{~GB} / \mathrm{s}$. The memory is constructed using DDR4 SDRAM chips which have the follow...

A C program, which initializes an integer array A of $4096$ elements to zero, is run on a computer with a direct-mapped data cache. The relevant details are provided belo...

Consider a $4$-way set-associative cache memory with a total of $16$ blocks. The Least Recently Used (LRU) policy is employed for block replacement. What is the number of...

Consider two cache organizations. The first is a $128$ KB 4-way set associative cache with a $64$byte block size. The second is of the same size and block size but is dir...

Consider a $4$-way set associative cache of size $64$ KB with a block size of $128$ bytes. The system uses a $36$-bit physical address. The number of bits required for th...

A computer system has a two-level cache (L1 and L2). The processor issues a memory request which is first sent to the L1 cache. The system has the following characteristi...

Processor A runs at $3$ GHz with a CPI of $1.5$. Processor B runs at $4$ GHz with a CPI of $1.2$. A program P , when compiled for Processor A , has $1 \times 10^9$ instru...

A machine has $16$-bit instructions. An address field takes $5$ bits. The machine uses an expanding opcode scheme. If there are $12$ two-address instructions and $150$ on...

Which of the following characteristics is a primary advantage of a hardwired control unit when compared to a microprogrammed control unit?EASE OF MODIFICATION HIGHER OPER...

In a computer system with a $32$-bit physical address, the address is broken down for cache mapping as follows: Tag = $18$ bits, Index (Set) = $8$ bits, Offset = $6$ bits...

A number is represented in IEEE 754 single-precision floating-point format as the hexadecimal value $\text{C22F0000}$ . What is the decimal value of this number?$-43.75$ ...

A system with a $1$ GHz CPU uses DMA to transfer data from a device at a rate of $50 \mathrm{MB} / \mathrm{s}$. The data is transferred in $32$ KB blocks. The DMA setup r...

An instruction $\text{MUL (R3)+, R4}$ is executed. This instruction fetches an operand from the memory location pointed to by register R3, performs the multiplication wit...

A processor uses a $32$-bit physical address. It has a $128 \mathrm{~KB}, 4$-way set associative L1 cache with a block size of $64$ bytes. What is the number of bits in t...

A six-stage pipeline processor has the stages: Fetch (FE), Decode (DE), Register Read (RR), Execute (EX), Memory Access (MA), and Write Back (WB). Each stage takes $1$ cl...

A direct-mapped cache memory of $1$ MB has a block size of $256$ bytes. The cache has an access time of $3$ ns and a hit rate of $94 \%$. During a cache miss, a $256$-byt...

A five-stage instruction pipeline has the stage delays of $150, 120, 160, 140$ and $130$ nanoseconds respectively. Registers that are used between the stages have a delay...

A 16-bit processor uses instructions with the following format:Opcode (4 bits) | Dst Register (3 bits) | Base Register (3 bits) | Offset (6 bits)The opcode $0 \times 9$ s...

An instruction's execution is divided into $5$ stages with the following individual stage delays:Instruction Fetch (IF): $10$ nsInstruction Decode (ID): $8$ nsExecute (EX...

Consider a system with a $2$-level cache. The access times of Level $1$ cache, Level $2$ cache, and main memory are $2 \mathrm{~ns}, 20 \mathrm{~ns}$, and $450$ ns , resp...