question related to gate 2008_67 (complex question)

Question

Question related to: gate 2008_67

Here is the question: https://gateoverflow.in/490/gate2008_67?show=61309#c61309

"So, in the given question, a main memory page frame is fetched with 24 bits of address and 12 offset bits, while the page frame corresponding to a third level page will be fetched using 25 bits of address and 11 offset bits (9 bits from VA + 2 bits for 4 bytes of PTE)."

So is my following conclusion correct(and consequently the understanding of the concept)?

1) There are 2^25 3rd level page tables.

2)There are still 2^9 entries in each 3rd level page table,but each page entry has 4 bytes,so offset(the size) becomes 2^11, and 4 bytes is 32 bits, we are using only 24 bits out of 32 for addressing page frames?

3)There are 2^25 2nd level page tables,There are still 2^9 entries in each 2nd level page table, PTE size is 4 bytes, so 32 bits are present but we are using only 25 bits out of 32 bits to address the 3rd level page tables(because we found out that there are 2^25 3rd level page tables)?

4)There are (2^36/((2^2)*(2^2)))= 2^32 1st level page table,each table has only 4 entries, but each page table entry contains 25 bits to address 2nd level page table?

5) So in layman terms, before we were going from left to right to calculate and splitting up the page tables for virtual address calculation, now we are doing up the reverse, for accommodating the page frames,the no of page tables do not remain the same at various levels,only thing remaining constant is the no of entries of page tables at each level and the PTE size, so we can calculate the offset bit for calculating the no of page tables possible?

Please correct my concept,at any level,where i went wrong.

Answer 1

1) There are 2^25 3rd level page tables.

Yes.

2)There are still 2^9 entries in each 3rd level page table,but each page entry has 4 bytes,so offset(the size) becomes 2^11, and 4 bytes is 32 bits, we are using only 24 bits out of 32 for addressing page frames?

512 entries, each entry 32 bits, only 24/32 bits used for addressing. - there is no offset bits here, we address using 32 bits which corresponds to each PTE and not individual bytes.

3)There are 2^25 2nd level page tables,There are still 2^9 entries in each 2nd level page table, PTE size is 4 bytes, so 32 bits are present but we are using only 25 bits out of 32 bits to address the 3rd level page tables(because we found out that there are 2^25 3rd level page tables)?

Yes, correct.

4)There are (2^36/((2^2)*(2^2)))= 2^32 1st level page table,each table has only 4 entries, but each page table entry contains 25 bits to address 2nd level page table?

If there are $2^{32}$ 1st level page tables, then who is selecting one among them? We have only "index bits" given for this. So, this means there is a single first level page table. You can see the below figure for a 2 level paging.

Comments

There are 2^25 3rd level page tables or there are There are 2^25 3rd level page tables possible??

The entire physical memory does not contain the third level page tables after all? Am i wrong sir?

---

@Sushmita Of course -- they are the maximum possible. Or we can say the possible address range can span that much and so we need so many address bits.

---

thanx sir, sorry my mind got really nonplussed. It was such a silly question :)