241 views

1 Answer

Best answer
3 votes
3 votes

Let us see one by one :

a) For generator and propogator functions :

n AND and n XOR gates..So 2n gates required the output of which will be fed to carrylookahead circuit..

b) For carry lookahead circuit :

It is a 2 level implementation with n(n+1)/2 AND gates and n OR gates.

So total gates required in carry lookahead circuit = n(n+1)/2  + n

                                                                      = ( n2 + 3n) / 2

c) Finally for generating sum bits :

For sum bits which will be n in no , hence we need n XOR gates..

So total number of gates required for carry lookahead adder  = 2n + (n2 + 3n) / 2 + n

                                                                                        =  (n2 + 3n) / 2 + 3n

                                                                                        =  (n+ 9n) / 2

Hence the correct answer is option B)..

selected by

Related questions

647
views
0 answers
0 votes
dileswar sahu asked Jan 22, 2017
647 views
how decoder work?(A and B here which one is LSB & MSB bez not mention).......plz someone explain
432
views
1 answers
0 votes
dileswar sahu asked Nov 22, 2016
432 views
How many minimum number of 2:1 multiplexer required to implement half substractor??
432
views
1 answers
2 votes
dileswar sahu asked Nov 19, 2016
432 views
plz someone draw its circuit,how it work....
510
views
1 answers
2 votes
dileswar sahu asked Nov 18, 2016
510 views
Consider a MOD 555 upcounter, the number of clock pulses for which MSB of the counter is ‘1’ is ______.