DMA problem

Question

A computer consists of a CPU and an I/O device D connected to main memory M via a shared bus with a data bus width of one word (16-bits). The CPU can execute a maximum of 10⁶ instructions per second. An average instruction requires five processor cycles, three of which use the memory bus. A memory read or write operation uses one processor cycle. Suppose that the CPU is continuously executing “background” programs that require 95% of its instruction execution rate but not any I/O instructions. Assume that one processor cycle equals one bus cycle. Now suppose that very large blocks of data are to be transferred between M and D.
Calculate I/O data transfer rate, in words per second possible through D if DMA transfer is used [ Assume that the DMA module can use all of these cycles, and ignore any setup or status‐checking time] ?

1.   2.15 x 10⁶
2.   3.15 x 10⁶
3.   1.15 x 10⁶
4.   4.15 x 10⁶

Answer 1

It is given that on an average an instruction requires 6 cycles and the CPU is busy 95% of the time in executing those instructions. Out of these 6 cycles, 3 cycles are needed for memory operations. During this time DMA cannot access the memory.

So only 3 cycles are left for DMA to use for 95% of the time. For 95% time DMA uses
0.95∗3 cycles

For rest 5% time, CPU isn't executing instructions, so all cycles are available, so DMA uses 0.05∗6 cycles
Total cycles available for DMA = (0.05∗6+0.95∗3) cycles

In 1second, CPU can execute 10^6 instructions. So rate of transfer = 10^6∗(0.05∗6+0.95∗3)=3.15∗10⁶