Test by Bikram | Mock GATE | Test 2 | Question: 26

Question

The designers of a computer must select a cache system. They have two options.

In first design they uses a direct-mapped cache containing $2$ words per cache line. It would have an instruction miss rate of $3%$ and a data miss rate of $8%$.

In second design they uses a $2$-way set associative cache containing $8$ words per cache line. It would have an instruction miss rate of $1%$ and a data miss rate of $4%$.

For each design, there will be approximately $0.5$ data references on average per instruction. The cache miss penalty in clock cycles is $8$ + cache line size in words; for example, the penalty with $1$-word cache lines would be $8 + 1 = 9$ clock cycles.

Let $D1 =$ cycles wasted by First Design on cache miss penalties (per instruction)

Let $D2 =$ cycles wasted by Second Design  on cache miss penalties (per instruction)

On average, how many clock cycles will be wasted by each on cache miss penalties?

• A. $D1 = 1.10, D2 = 0.96$
• B. $D1 = 0.70, D2 = 0.40$
• C. $D1 = 1.10, D2 = 0.40$
• D. $D1 = 0.70, D2 = 0.48$

Comments

calculation

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@sheshang

please see the best chosen answer for calculation , you can also read my answer .

Answer 1

No of instruction per instruction is 1 and no of data per instruction is 0.5

Direct-mapped cache containing 2 words per cache line. It would have an instruction miss rate of 3% and a data miss rate of 8%.
Miss penality = 0.03(8+2) + 0.08(8+2)/2 = 0.30 + 0.40 = 0.70

2-way set associative cache containing 8 words per cache line. It would have an instruction miss rate of 1% and a data miss rate of 4%.
Miss penality = 0.01(8+8) + 0.04(8+8)/2 = 0.16 + 0.32 = 0.48

Comments

more explanation pls

Answer 2

For these designs,

let p equal the cache miss penalty, in clock cycles, and let m_i and m_d indicate the instruction and data miss rates, respectively.

Then the total time spent on penalties, for an average instruction, is p * (1 * m_i + 0.5 m_d), since there are about 0.5 data references per instruction.

Consequently, the total penalty for D1 and D2, are 0.70 and 0.48, respectively.

Comments

@Bikram Sir, Can you please provide any references to read about instruction miss rate/

Can you tell what instruction miss rate is?