GATE2017 EC Digital

Question

Comments

@anusha it hink last ex-or gate for carry should b or gate
https://gateoverflow.in/8250/gate2015-2_48

---

okey, assuming its OR gate, answer according to u?

---

I think 90

---

We get sum after 40ns, carry after 45ns for one adder. For 4 bit, the delay is 3*45 + 40 =175ns

---

@gateset
why arent u waiting for carry bit to stabilize?

---

@anusha you are right, sum gets stabilised at 175ns, carry gets stabilised at 180ns.

---

180 should be right answer.

plz comment if not agree!

---

i feel the same that answer is 180

---

??? wrong ??

---

Or wait for full output <S,C> of prev adder?

---

as they mentioned ripple carry addr , i think we need to wait until one full adder completely gives the output
simila ques https://gateoverflow.in/8250/gate2015-2_48
here accordin to oficial key we need to assume that we can do 2nd full adder only when first full adder gives the complete o/p

---

Ok. Thanks !

---

Please check it:

If all are full adders:

First adder will give Sum after 40 nsec and Carry after 45 nsec ;

total delay = 4×45 = 180

If we choose first adder as half adder (as no need to add carry) : delay= 15+3×45 = 150 nsec

(because they have not mentioned all are full adder)

---

@target2017

yes ! this could be the case.

---

^Gabbar,target why we r nt taking 20 for half adder

---

at 20 sum is available .at 15 carry is available as input to second full adder . as per half adder. 20 time unit can be overlapped by other full adders...that why.

---

^ but in ripple-carry adder each adder must wait for the full output from the previous adder.

---

according to question i assume it . can u give me any reference for it ??

---

see this https://gateoverflow.in/8250/gate2015-2_48

---

yes! @saurabh rai according to gate ans key..we need to assume...But according to ripple adder, carry is propagated why should we take care about sum ?? why we have to wait for full output ?? it time permits plz comment..

 Thanks for pointing out mistake!

---

i think it should wait for carry only nt for sum bcoz carry is propagated

---

does anybody has an answer yet??

according to gate answer key we need to wait for full adder

but according to books just waiting for carry is sufficient

what to use?

---

@Debashish Though previous GATE key says otherwise, since the given question has the picture of the adder implementation, I would certainly go with your answer of 120. But I I'm only 90% sure.

---

yes @Debashish and @Arjun sir

according to every official site of IIT's about ripple carry adder, they are doing the same as what Debashish has done

So, 120 is correct ans

ref: http://iitkgp.vlab.co.in/?sub=38&brch=120&sim=483&cnt=664

---

and other webside mentioned the question in another way



what about this one?

---

Stablility of ripple carry adder => Worst case delay of ripple carry adder .

web.cs.ucla.edu/Logic_Design/SLPDF/ch10.pdf

---

I think we should answer 120 as Arjun sir said its conceptually correct at least then we can challenge the answer sheet if they solved it differently

---

@Anusha If the question is like that then we should see when the output stops changing.

---

This is the actual GATE Question, all are Full Adders

Answer given is 50 in the Key

https://drive.google.com/file/d/0ByPcpxjSfRuVVWd4c184YWJuUEk/view

https://drive.google.com/file/d/0ByPcpxjSfRuVTldxaDBWUE45ZE0/view

Answer 1

 Delay for sum is 2*XOR = 2*20  = 40ms
 Delay for carry is 1xor+1and+1or=20+15+10=45 ns
in ripple-carry adder each adder must wait for the full output from the previous adder.
hence delay for S₃= 3*45+40=175 ns
delayfor last carry= 4*45=180 ns
nd it is asking for stable o/p so it should b 180 ns .

Comments

for first bit there is no carry input, can we use half adder only for first bit?

---

@anusha i think u r right ....
edited

---

You could have made the answer more simple!

Answer 2

If XOR= 20

AND= 15

OR=10

Shouldn't the answer be 4*45=180ns?

Comments

Where is OR gate in the figure?Are we referring to same figure given above?

And what is 10 ns delay for OR?I dont see it is mentioned in question?

Please help

---

they gave XOR gate by mistake in the figure. to get carry we shud use OR gate ryt?
and there are 3 delays given.. we assumed the 3rd delay to be OR gate delay

Answer 3

The question is straight out of Salivahanan! 
So the stable output is generated by the last carry bit C4 = 4 * Tp, the in this 4 bit binary adder, as the propagation delay is clearly (20+15+10)nsec  = 45nsec so,C4 = 4 * 45 = 180nsec 

Answer 4

The answer should be 50 ns.