7 votes 7 votes Digital Logic digital-logic + – Anusha Motamarri asked Feb 6, 2017 Anusha Motamarri 3.5k views answer comment Share Follow See all 29 Comments See all 29 29 Comments reply saurabh rai commented Feb 6, 2017 reply Follow Share @anusha it hink last ex-or gate for carry should b or gate https://gateoverflow.in/8250/gate2015-2_48 0 votes 0 votes Anusha Motamarri commented Feb 6, 2017 reply Follow Share okey, assuming its OR gate, answer according to u? 0 votes 0 votes target2017 commented Feb 6, 2017 reply Follow Share I think 90 0 votes 0 votes Samujjal Das commented Feb 6, 2017 reply Follow Share We get sum after 40ns, carry after 45ns for one adder. For 4 bit, the delay is 3*45 + 40 =175ns 0 votes 0 votes Anusha Motamarri commented Feb 6, 2017 reply Follow Share @gateset why arent u waiting for carry bit to stabilize? 0 votes 0 votes Samujjal Das commented Feb 6, 2017 i edited by Samujjal Das Feb 6, 2017 reply Follow Share @anusha you are right, sum gets stabilised at 175ns, carry gets stabilised at 180ns. 0 votes 0 votes papesh commented Feb 6, 2017 reply Follow Share 180 should be right answer. plz comment if not agree! 2 votes 2 votes Anusha Motamarri commented Feb 6, 2017 reply Follow Share i feel the same that answer is 180 0 votes 0 votes dd commented Feb 6, 2017 reply Follow Share ??? wrong ?? 0 votes 0 votes dd commented Feb 6, 2017 reply Follow Share Or wait for full output <S,C> of prev adder? 0 votes 0 votes Anusha Motamarri commented Feb 6, 2017 reply Follow Share as they mentioned ripple carry addr , i think we need to wait until one full adder completely gives the output simila ques https://gateoverflow.in/8250/gate2015-2_48 here accordin to oficial key we need to assume that we can do 2nd full adder only when first full adder gives the complete o/p 2 votes 2 votes dd commented Feb 6, 2017 reply Follow Share Ok. Thanks ! 0 votes 0 votes target2017 commented Feb 7, 2017 reply Follow Share Please check it: If all are full adders: First adder will give Sum after 40 nsec and Carry after 45 nsec ; total delay = 4×45 = 180 If we choose first adder as half adder (as no need to add carry) : delay= 15+3×45 = 150 nsec (because they have not mentioned all are full adder) 0 votes 0 votes papesh commented Feb 7, 2017 reply Follow Share @target2017 yes ! this could be the case. 0 votes 0 votes saurabh rai commented Feb 7, 2017 reply Follow Share ^Gabbar,target why we r nt taking 20 for half adder 0 votes 0 votes papesh commented Feb 7, 2017 reply Follow Share at 20 sum is available .at 15 carry is available as input to second full adder . as per half adder. 20 time unit can be overlapped by other full adders...that why. 0 votes 0 votes saurabh rai commented Feb 7, 2017 reply Follow Share ^ but in ripple-carry adder each adder must wait for the full output from the previous adder. 0 votes 0 votes papesh commented Feb 7, 2017 reply Follow Share according to question i assume it . can u give me any reference for it ?? 0 votes 0 votes saurabh rai commented Feb 7, 2017 reply Follow Share see this https://gateoverflow.in/8250/gate2015-2_48 0 votes 0 votes papesh commented Feb 7, 2017 reply Follow Share yes! @saurabh rai according to gate ans key..we need to assume...But according to ripple adder, carry is propagated why should we take care about sum ?? why we have to wait for full output ?? it time permits plz comment.. Thanks for pointing out mistake! 0 votes 0 votes saurabh rai commented Feb 7, 2017 reply Follow Share i think it should wait for carry only nt for sum bcoz carry is propagated 0 votes 0 votes Pankaj Joshi commented Feb 7, 2017 reply Follow Share does anybody has an answer yet?? according to gate answer key we need to wait for full adder but according to books just waiting for carry is sufficient what to use? 0 votes 0 votes Arjun commented Feb 9, 2017 reply Follow Share @Debashish Though previous GATE key says otherwise, since the given question has the picture of the adder implementation, I would certainly go with your answer of 120. But I I'm only 90% sure. 0 votes 0 votes Lokesh . commented Feb 9, 2017 reply Follow Share yes @Debashish and @Arjun sir according to every official site of IIT's about ripple carry adder, they are doing the same as what Debashish has done So, 120 is correct ans ref: http://iitkgp.vlab.co.in/?sub=38&brch=120&sim=483&cnt=664 1 votes 1 votes Anusha Motamarri commented Feb 9, 2017 reply Follow Share and other webside mentioned the question in another way what about this one? 0 votes 0 votes Kapil commented Feb 9, 2017 reply Follow Share Stablility of ripple carry adder => Worst case delay of ripple carry adder . web.cs.ucla.edu/Logic_Design/SLPDF/ch10.pdf 0 votes 0 votes Pankaj Joshi commented Feb 9, 2017 reply Follow Share I think we should answer 120 as Arjun sir said its conceptually correct at least then we can challenge the answer sheet if they solved it differently 0 votes 0 votes Arjun commented Feb 9, 2017 reply Follow Share @Anusha If the question is like that then we should see when the output stops changing. 0 votes 0 votes aakashpreetam commented May 24, 2018 reply Follow Share This is the actual GATE Question, all are Full Adders Answer given is 50 in the Key https://drive.google.com/file/d/0ByPcpxjSfRuVVWd4c184YWJuUEk/view https://drive.google.com/file/d/0ByPcpxjSfRuVTldxaDBWUE45ZE0/view 0 votes 0 votes Please log in or register to add a comment.
4 votes 4 votes Delay for sum is 2*XOR = 2*20 = 40ms Delay for carry is 1xor+1and+1or=20+15+10=45 ns in ripple-carry adder each adder must wait for the full output from the previous adder. hence delay for S3= 3*45+40=175 ns delayfor last carry= 4*45=180 ns nd it is asking for stable o/p so it should b 180 ns . saurabh rai answered Feb 6, 2017 • edited Feb 6, 2017 by saurabh rai saurabh rai comment Share Follow See all 6 Comments See all 6 6 Comments reply Show 3 previous comments target2017 commented Feb 6, 2017 reply Follow Share for first bit there is no carry input, can we use half adder only for first bit? 0 votes 0 votes saurabh rai commented Feb 6, 2017 reply Follow Share @anusha i think u r right .... edited 0 votes 0 votes Namit Dhupar commented Nov 6, 2017 reply Follow Share You could have made the answer more simple! 0 votes 0 votes Please log in or register to add a comment.
3 votes 3 votes If XOR= 20 AND= 15 OR=10 Shouldn't the answer be 4*45=180ns? Vijay Thakur answered Feb 6, 2017 Vijay Thakur comment Share Follow See all 2 Comments See all 2 2 Comments reply rahul sharma 5 commented Feb 7, 2017 reply Follow Share Where is OR gate in the figure?Are we referring to same figure given above? And what is 10 ns delay for OR?I dont see it is mentioned in question? Please help 0 votes 0 votes Anusha Motamarri commented Feb 7, 2017 reply Follow Share they gave XOR gate by mistake in the figure. to get carry we shud use OR gate ryt? and there are 3 delays given.. we assumed the 3rd delay to be OR gate delay 0 votes 0 votes Please log in or register to add a comment.
0 votes 0 votes The question is straight out of Salivahanan! So the stable output is generated by the last carry bit C4 = 4 * Tp, the in this 4 bit binary adder, as the propagation delay is clearly (20+15+10)nsec = 45nsec so,C4 = 4 * 45 = 180nsec Namit Dhupar answered Nov 6, 2017 Namit Dhupar comment Share Follow See all 0 reply Please log in or register to add a comment.
0 votes 0 votes The answer should be 50 ns. Amit puri answered Aug 29, 2018 • edited Aug 30, 2018 by Amit puri Amit puri comment Share Follow See all 0 reply Please log in or register to add a comment.