1 1 vote The sum S of A and B in a half Adder can be implemented by using K NAND gates. The value of K is a) 3 b) 4 c) 5 d) None of these Digital Logic isro-ece digital-logic + – sh!va 4.2k views answer comment Share Follow Print 0 reply Please log in or register to add a comment.
2 2 votes Sum is given by EX-OR operation. So we need to simply implement EX-OR gate by NAND gate. A Xor B = A'B + AB' = (A' + B')(A+B) = A(AB)' + B(AB)' = ( A(AB)' + B(AB)' ) ' ' = ( (A(AB)')' + (B(AB)')' ) ' = 4 NAND gates. Rahul Jain25 answered Mar 3, 2017 Rahul Jain25 comment Share Follow See 1 comment 1 1 comment reply $ruthi commented Jul 14, 2017 reply Follow flag We need 5 NAND gates to implement half adder. Sum implementation is done using 4 NAND gates (XOR operation needs 4 NAND gates) Carry implementation needs 1 NAND gate SO, totally we need 5 NAND gates 1 1 replyShare Please log in or register to add a comment.
2 2 votes Sum of HALF ADDER IS A XOR B which can be represented using 4 nand gate as following: i Neeraj Chandrakar answered Jul 25, 2017 Neeraj Chandrakar comment Share Follow 0 reply Please log in or register to add a comment.
