Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 28

Question

Consider the following Micro-operations:

$\begin{array}{|l|l|} \hline \text{MAR} & \leftarrow IR \text{[address]} \\ \hline \text{MBR} & \leftarrow \text{Memory} \\ \hline IR \text{[address]} & \leftarrow \text{MBR[address]} \\ \hline \end{array}$

• $IR \text{ [ address]} =$ The address field of the instruction .
• $\text{MAR } =$ Memory Address Register
• $\text{ MBR }=$ Memory Buffer Register

The given micro-operations describes :

• A. Interrupt Cycle
• B. Fetch Cycle
• C. Execute Cycle
• D. Indirect Cycle

Comments

Can you please explain this micro-operations?

We read the address from the instruction's address field. Then we transferred the contents of that address to the memory location to MBR

I am not able to get the last part?

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@rahul sharma 5

This is the meaning of the last part :

IR [ address ] <-- MBR [ address]

---> The Instruction Register is updated from Memory Buffer Register .  IR is now contain a direct memory address rather than indirect address .

so these micro operations represents a indirect cycle .

Answer 1

• Micro-operation 1 :

1. MAR <-- IR [ address] 

---> The address field of the instruction is transferred to Memory Address Register ( MAR ) , this address field is then used to fetch the address of the operand.

• Micro-operation 2 :

2. MBR <--- Memory

--> After fetching the memory address, we transferred the contents/value of that address from memory to MBR .

• Micro-operation 3 :

3. IR [ address ] <-- MBR [ address]

---> The Instruction Register is updated from Memory Buffer Register .  IR is now contain a direct memory address rather than indirect address .

So, these 3 micro operations perform Indirect cycle . Which is option D.

This is not a fetch cycle as in fetch PC is required , neither Interrupt nor execute cycle as there is no instructions like add,sub etc exists ..

Comments

it can be found anywhere, google it out or you can see this

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where is indirect cycle? the link which you shared is instruction cycle.

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But indirect should not be like this ? 

1. $IR[addr]\rightarrow MAR$
2. $M[MAR]\rightarrow MBR$
3. $MBR\rightarrow MAR$
4. $M[MAR]\rightarrow MBR$
5. $MBR\rightarrow ACC$