in Digital Logic
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Given an S-R flip-flop in the 0 state, what is the sequence of inputs necessary to cause the following sequence of states:

0, 0, 1, 1, 0, 0, 1, 0, 1.
in Digital Logic
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We can design it using 4 SR Flip flops Synchronous Counter.

And Inputs sequence will be:-

0000 -> 0010 -> 0001 -> 0011 -> 0100 -> 0110 -> 0101 -> 1000 -> 0111 -> 0000( initial state ).

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@Shubhanshu I think the question is just asking for the SR inputs. And not to design a counter.
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