According to the question , when a cache miss occurs , following course of action will be taken..Let us write the delay for each action :
a) Detecting cache miss time : It is given the same as cache hit time .Hence time taken here = 5 ns
b) Transferring first word of the main memory block to cache line : Here given time = 90 ns
c) Transferring remaining words from main memory to cache line :
Here we need to find the number of words that can be stored in one cache line.
Hence number of words = Line size / Word size
= 64 B / 2 B
= 32
Hence number of words remained to be sent = 32 - 1 = 31
Latency to transfer each of these words given = 10 ns
Hence total time taken to transfer these words = 31 * 10
= 310 ns
d) Re executing memory fetch instruction which will lead to cache hit : For that again we need time equivalent to cache hit latency..Hence time taken here = 5 ns
Hence total time taken = 5 + 90 + 310 + 5
= 410 ns
Hence total time incurred should be 410 ns in case of cache miss as per the events mentioned in the question..