Comp.Architecture-2 [closed]

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Here $128$ block actually refers to Lines right?
So it should be $8+4+7=19$ Assume memory is word addessable?Thanks!

closed with the note: Wrong interpretation

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2
Set number = cache lines/k = 128/4 = 32 hence set number bits = 5

total bits = 8+5+4 = 17

it should be 17 bits ..

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Work done by me :for write it will always be $100ns$ Now for read :$20+0.2*100=40$ Total =$0.7*40+0.3*100=58$
My work: $1+0.1*5+0.05*50=4ns$ Now please give me reasoning about : missing in $L1$ i will access $L2$ and i did that now When i am missing in $L2$ isn`t this obvious that i have actually missed in $L1$ or should i mention it by $0.05*0.1*50$ Thanks!