Register

Does Load and Store instruction Require ALU Operation ?

625 views

Please log in or register to answer this question.

Voting & Accepting an answer helps improve the community
← Previous · Turing machineNext → · AVL tree
← Previous in category · Associative mapping ...Next in category → · Previous Year Questi...
Position:
Show:

Related questions

0 0 votes
1 1 answer
1.1k
1.1k views
amiteshKeshari asked Aug 24, 2023
1,147 views
Consider a one word instruction ADD R2,@R1 executed on Hypothetical CPU R1 and R2 are processing registers. Fetching operation takes 2 clock cycles, memory operand read takes 2 clock cycles and any ALU operation takes one clock cycles and extra clock is not required for storing the result in destination regiseter. No. of memory cycles needed to complete the insturction cycle of the above ADD R2,@R1 is .........
4 4 votes
1 1 answer
1.2k
1.2k views
yes asked Nov 20, 2015
1,219 views
The ALU, the bus and all the register are identical in size. the instruction "memory write"
The ALU, the bus and all the register are identical in size. The instruction "memory write" has the register transfer interpretation M[(R1)] ← R2. The minimum number...
1 1 vote
1 1 answer
1.1k
1.1k views
radha gogia asked Oct 19, 2015
1,086 views
How does relocation register differ in case of load time binding and execution time binding ?
I have gone through this link but still I am unable to get what is it actually trying to convey , when binding is done at execution time then obviously before it we must ...