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asked in CO and Architecture by Active (4.8k points) | 97 views
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I am getting 4.4 cycles.
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ans is given as 13.02
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post solution
+1

I don't have solution with me. It's actually from here(5th question): https://www.cse.buffalo.edu//~stevko/courses/cse490/spring11/files/midterm-sol.pdf

This question was also asked in Virtual GATE full length test.

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Best answer
$L_3$ Miss penalty $=$ Memory hit time $= 100\space cycles$
$L_3$ hit time$ = 50$ $cycles$

$L_3$ hit ratio $= 50$%

So, $L_2$ miss penalty $= \frac{50}{100}$ x $L_3$ $hit$ $time + \frac{50}{100}$ x $L_3$ $miss$ $penalty$

$ = \frac{50}{100}$ x $100 + \frac{50}{100}$ x $50 = 75$ $cycles$

 

$L_2$ hit time $= 8$ $cycles$

$L_2$ hit ratio $= 80$%

So, $L_1$ miss penalty $= \frac{80}{100}$ x $L_2$ $hit$ $time$ $+ \frac{20}{100}$ x $L_2$ $miss$ $penalty$

               $= \frac{80}{100}$ x $8 + \frac{10}{100}$ x $75  = 21.4$ $cycles$

 

$TLB$ hit time $= 1$ $cycle$

$TLB$ miss penalty $=$ Page table walk and TLB update time $= 200$ $cycles$
$TLB$ hit ratio $= 95$%
So, $TLB$ $access$ $time = TLB$ $hit$ $time$ x $\frac{95}{100} + (TLB$ $hit$ $time + TLB$ $miss$ $penalty)$ x $\frac{5}{100}$
 $= 1$ x $\frac{95}{100} + (1+200)$ x $\frac{5}{100} = 11$ $cycles$

 

$L_1$ hit time $= 1$ $cycle$

$L_1$ hit ratio $= 95$%

So, Average memory access time $= TLB$ $access$ $time + (\frac{95}{100}$ x $L_1$ $hit$ $time + \frac{5}{100}$ x $L_1$ $miss$ $penalty)$

$= 11 + (\frac{95}{100}$ x $1 + \frac{5}{100}$ x $21.4)$

$= 11 + 2.02 = 13.02$ $cycles$.
answered by Active (1.4k points)
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