3 votes 3 votes Delay of AND gate = 1ns, FF = 2ns. What is the maximum clock rate possible to apply so that counter will work satisfactorily? a) 143 MHz b) 200 MHz c) 333 MHz Digital Logic digital-logic clock-frequency + – Tuhin Dutta asked Jan 18, 2018 • edited Jan 19, 2018 by Tuhin Dutta Tuhin Dutta 960 views answer comment Share Follow See all 18 Comments See all 18 18 Comments reply srestha commented Jan 19, 2018 reply Follow Share Ans B)200 right?? 0 votes 0 votes hs_yadav commented Jan 19, 2018 reply Follow Share here delay for flip-flop and and gate is required...... for counter to work perfectly time period of clock cycle should be:- $Tt>=3*$FF_DELAY$+$and gate delay 0 votes 0 votes Ashwin Kulkarni commented Jan 19, 2018 reply Follow Share @Tuhin delay of flip flop and AND gate is also required here. 0 votes 0 votes Ashwin Kulkarni commented Jan 19, 2018 reply Follow Share @hs No need to do 3*delay_FF because only 2nd FF is dependent on 1st one. Third will work simultaneously with first one. SO it should be 1/frq >= 2*FF_delay + Delay_combi.circut. 4 votes 4 votes srestha commented Jan 19, 2018 reply Follow Share But we can get frequency of the FF right? And from there we can get clock rate 0 votes 0 votes Tuhin Dutta commented Jan 19, 2018 reply Follow Share @Ashwin, yeah forgot to mention that. 0 votes 0 votes Anu007 commented Jan 19, 2018 reply Follow Share i am getting 143. 0 votes 0 votes hs_yadav commented Jan 19, 2018 reply Follow Share ashwin,,, yes, got it .... 0 votes 0 votes Tuhin Dutta commented Jan 19, 2018 reply Follow Share @Ashwin, until the output from the AND gate goes to the input of the third flip flop and the inverted output from the third FF goes to the input of first FF, does one cycle complete? 0 votes 0 votes Ashwin Kulkarni commented Jan 19, 2018 reply Follow Share ANswer is $200Mhz$ 0 votes 0 votes Anu007 commented Jan 19, 2018 reply Follow Share Hs yadav you were correct previously, till input come to Last FF we have to wait no matter clock is on or off. 0 votes 0 votes Tuhin Dutta commented Jan 19, 2018 reply Follow Share @Ashwin, yes answer is correct but my doubt is that in 5ns does one cycle complete? Shouldn't it take 7ns for "proper functioning"? 0 votes 0 votes Ashwin Kulkarni commented Jan 19, 2018 reply Follow Share @Anu sir but clock is simultaneously applied to 1st and 3rd so they'll activate at the same time. What's the answer @tuhin? 1 votes 1 votes Tuhin Dutta commented Jan 19, 2018 reply Follow Share @Anu sir, I also got 143MHz since I felt for one cycle to complete output from the last flip flop should propagate to 1st FF. 0 votes 0 votes Ashwin Kulkarni commented Jan 19, 2018 reply Follow Share Yes in 5ns cycle will be completed because 3rd FF will be activated when 1st gets activated. 2 votes 2 votes Tuhin Dutta commented Jan 19, 2018 reply Follow Share As per Made Easy answer is 200MHz. Had been the And Gate applied to the last FF then it would be 5ns for 1 clock cycle to complete 0 votes 0 votes Anu007 commented Jan 19, 2018 reply Follow Share yes ashwin it will be 5nsec. i was confused earlier . :) 1 votes 1 votes srestha commented Jan 19, 2018 reply Follow Share @Ashwin how u calculated? I need to chk it 0 votes 0 votes Please log in or register to add a comment.
0 votes 0 votes Tclock>=Tpropagation-delay= 2*Tff + Tand-gate=5ns Frequency=1/Tclock=1/5ns=200MHz suvradip das answered Sep 5, 2020 suvradip das comment Share Follow See all 0 reply Please log in or register to add a comment.