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MadeEasy Test Series 2018: CO & Architecture - Cache Memory

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Answer given is 3.  But I think the answer should be 4 

conflict miss will occur in 100,108,114,1C7,128,1B5,100,108,1C7 (highlighted misses)

My approach: I found that no. of sets is 2 and only 1 bit will be sufficient.

Based on the binary form of the cache request given.I found that conflict misses to be in those highlighted areas.

Need your help if I am doing wrong somewhere or may be answer is incorrect.

Thanks in advance for your help.

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