MadeEasy Test Series 2018: Digital Logic - Digital Counter

Question

answer given is 100KHz

Answer 1

all flip flops are clocked with same clock so their delay is max(5,4,3)=5micro sec

similarly all the nad gate are producing output after getting their input from flip flops so their max delay is also 5 micro sec (due to flip flops are synchronously arranged) so total delay =5+5 micro sec=10 micro sec

frequency =1/10micro sec

=0.1*10^6

=100000

=100Khz

Comments

Delay should be max(3+3+5, 3+4, 3)

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@minipanda @eyeamgj

when a clock pulse applied in this first 5 micsecs flip flops will give output and in next 6 microsec input will be ready for the next clock pulse.

So, after each 11 microsec, next clock pulse can be applied.

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Rishabh Gupta 2 and Manu Thakur Ohk..i think i got it..Thank you

But can you please tell me one thing..if the clock connections were asynchronous then the delays would get added or not? Here the FF's are getting triggered simultaneously and producing the o/p based on what the previous FF has produced in the previous clock pulse right?