Log In
39 votes

In the sequential circuit shown below, if the initial value of the output $Q_1Q_0$ is $00$. What are the next four values of $Q_1Q_0$?


  1. $11$, $10$, $01$, $00$
  2. $10$, $11$, $01$, $00$
  3. $10$, $00$, $01$, $11$
  4. $11$, $10$, $00$, $01$
in Digital Logic
edited by
I think, timing diagrams are best way to solve problems of asynchronous counters.

If see option clearly Q0 must be toggle on each clock, only option a is showing this 

i.e. 0->1->0->1->0->1

closer look :

when q1q0= 00 then next state 11 ( T1 T2 = 11 )

option b and c discard

now option D say after 00 --> 01 this  is  no possible  

so answer A

10 Answers

41 votes
Best answer

Option A.

$2^{nd}$ flip-flop will be active only when $1^{st}$ flip flop produces output $1.$ For clocks $2$ and $4$ old output is retained by Flip-Flop $2$.

$\begin{array}{c|c}T&Q_{n+1}\\\hline 0&Q_n\\1&\overline{Q_n}\end{array}$$\underset{\text{For rows 2 and 4, Clk for $T_1$ is 0 and hence old o/p is retained}}{\begin{array}{cc|cc}T_0&Q_{0}&T_1&Q_1\\\hline &0&&0\\\hline 1&1&1&1\\1&0&1&1\\1&1&1&0\\1&0&1&0\end{array}}$ $\begin{array}{c|c}Q_1&Q_{0}\\\hline1&1\\1&0\\0&1\\0&0\end{array}$

edited by
Still i have confusion  in this solution.Can anybody plzz make it more clear.

This is how A is the answer:

@neha_singh 2nd Flip-Flop will be active only when 1st Flip Flop produce output 1 . For clock 2 and 4 Old output is retained

see, clock of T1 will be triggered when Qchanges from 0-->1 as it is a positive edge triggered flip flop.


Such kind of question make more sense if we solve using timing diagram.

Please note that the FF indicated in the diagram are positive edge triggered and are asynchronous.

A very subtle hint given here is that the circuit is a flip-flop, and not latch. I was assuming it to be a latch.
Why are we considering present state of $Q_0$? shouldn't we take previous state of $Q_0$, for determining present state of $Q_1$ ??

@Rishabh Gupta 2 that is the same doubt which is annoying me! Have you found the answer to your question?

@cognoscenti... You are treating it as synchronous counter.. But this a asynchronous counter where the triggering of Q1 is dependent on the positive edge triggering of Q0 ,not on the clock directly.

Oh! got it. thanks @Cristine

It is an Asynchronous counter.
17 votes
answer - A

Initially Q0Q1 = 00

after first clock signal Q0 will be toggled and change to 1. It will activate clock of second FF in sequence and toggle that one as well.

Hence next output Q0Q1=11

Similarly next few sequences for Q0Q1 will be 01, 00

Hence answer sequence Q1Q0 will be 11,10,01,00
Can someone explain in detail ?

" after first clock signal Q0 will be toggled and change to 1 " - How is this possible ?

Logic 1 is constantly applying.. So how are you getting  01, 00 ?

Can you please explain it with boolean algebra ?

I am not getting the working

For $T$ flip-flop , next state equation $Q^+$ = $T\oplus Q$

when $T = 1$, $Q^+$ = $1\oplus Q = Q'$

Q0  Q1

0     0
1    1
0     1

Now ,  In first FF
 1 XOR (last Q0 = 0 )  =   1

 This activate 2 nd FF
  1  XOR ( last Q1 = 1 ) = 0

So the states are 00 , 11 , 01 , 10

Am I correct ?
Yes that is what you derived the sequence of $Q_0Q_1$ but in question they asked $Q_1Q_0$
Thanks :)
Activating the 2nd FF clock is ok but how can you get the o/p of 2nd FF in the same cycle? It should be the next +ve edge, when it should be updated (like we do in Up or Down counter, where the next bit's clock is dependant on the previous bit's edge..) So , as per that scene why cant be the o/p as 01,00,11... ? Please explain somebody....

I am also having same confusion. how can you get the o/p of 2nd FF in the same cycle? 

Please explain somebody.

@pc this is  +ve edge triggered flip flop and this flip flop  will be activated when clock pulse will be 1 .???

is it rt na ?????
T flip flop on 1 toggle the input.

So on Qo  =  1, Second flip flop receive 1 and toggle its output so it becomes also 1. So 11 is generated.

next Qo = 0 (again toggles its output) and 2nd flip flop recieve it and perform no change so Q1 = 1 unchanged. SO 10 generated.

In this fashion so on.

logic is on each edge trigger, 1st flip flop toggles and when 1st ff give 1 opt next ff will toggle otherwise it will remain unchanged. Very easy.

@kunal_chalotra , Sorry for late reply saw ur message right now only.
This might be helpful . Nice video . worth for 5 min :)

its k @pc  :)
5 votes

Since, Flip Flop T0 is clocked directly from main clock, Q0 will make transitions(toggle as it's T input is 1) whenever the clock pulse goes from 0 to 1 as flip flops are positive edge triggered.

Flip Flop T1's clock is depending on output of Flip Flop T0 which is Q0. Hence, whenever Q0 makes a transition from 0 to 1,Q1, will also make transition(toggle as it's T input is 1) .

As it it clear from timing diagram, the next four values of Q1 Q0 are 11, 10, 01 , 00. Ans (a)

4 votes

Asynchronous circuit, please correct me if iam wrong,.

2 votes
Despite all the excellent answers explaining the in depth working of the circuit, i will like to mention a trick, that is time saving too (specific to this question only).

Here, we can see that T Flip Flop is used and T flip flop will complement the current state when presented with input one, here the Flip Flop giving the output Q0 is connected to the clock, and is given constant input 1. So, Q0 will alternate with every clock pulse. Only option A satisfies this condition.
1 vote

From the timing diagram it is clear that this counter is Mod 3 ripple down counter.

So, counting goes as 00,11,10,01,00 (Option A)

Note : Transitions only occur at the positive edge of the clock as the Flip Flops are edge triggered.

1 vote

it's here

1 vote

$Q_{0Next} = T_{0}\oplus Q_{0} = 1\oplus Q_{0} = Q_{0}'\:;\:$ For every clock

$Q_{1Next} = T_{1} \oplus Q_{1} = 1 \oplus Q_{1} = Q_{1}'\:;\: $ When $Q_{0}:0 \:to\: 1$ (Because clock is positive edge triggered)

$Q_{1}$ $Q_{0}$ $Q_{1Next}$ $Q_{0Next}$
$0$ $0$ $1$ $1$
$0$ $1$ $0$ $0$
$1$ $0$ $0$ $1$
$1$ $1$ $1$ $0$

State diagram:

So, the correct answer is $(A)$.

edited by

Related questions

21 votes
4 answers
What is the boolean expression for the output $f$ of the combinational logic circuit of NOR gates given below? $\overline{Q+R}$ $\overline{P+Q}$ $\overline{P+R}$ $\overline{P+Q+R}$
asked Sep 29, 2014 in Digital Logic jothee 4.8k views
17 votes
2 answers
The Boolean expression of the output $f$ of the multiplexer shown below is $\overline {P \oplus Q \oplus R}$ $P \oplus Q \oplus R$ $P+Q+R$ $\overline{P+Q+R}$
asked Sep 29, 2014 in Digital Logic jothee 3.4k views
34 votes
2 answers
$P$ is a $16$-bit signed integer. The $2$'s complement representation of $P$ is $(F87B)_{16}$. The $2$'s complement representation of $8\times P$ is $(C3D8)_{16}$ $(187B)_{16}$ $(F878)_{16}$ $(987B)_{16}$
asked Sep 29, 2014 in Digital Logic jothee 6.3k views
35 votes
1 answer
The main memory unit with a capacity of $4$ $\text{megabytes}$ is built using $1M \times$ $\text{1-bit}$ DRAM chips. Each DRAM chip has 1K rows of cells with $1K$ cells in each row. The time taken for a single refresh operation is $100$ $\text{nanoseconds}$. ... in the memory unit is $100$ nanoseconds $100\times 2^{10}$ nanoseconds $100\times 2^{20}$ nanoseconds $3200\times 2^{20}$ nanoseconds
asked Sep 29, 2014 in Digital Logic jothee 9.1k views