A CPU has cache with block size 64 bytes. The main memory has k blocks, each being c bytes wide. Consecutive c byte chunks are mapped on consecutive blocks with warp around. All the k blocks may be accessed in parallel, but two accesses to the same block need to be serialized. A cahe block access may involve multiple iterations of parallel block accesses depending on the amount of data obtained by accessing all k blocks in parallel. Each iteration requires decoding the block numbers to be accessed in parallel which takes k/2 ns. The latency of one block access is 80ns. If c=2 and k=24 then latency of retrieving a cache block starting at address zero from main memory is
92ns 104ns 172ns 184ns
