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Assume the following performance characteristics on a cache read miss:

one clock cycle to send an address to main memory and four clock cycles to access a 32-bit word from main memory and transfer it to the processor and cache. What is the miss penalty if the cache line size is four words and a transfer is executed, with one clock cycle per word transfer?

What would be the answer if memory is not interleaved and word access is done sequentially from main memory?

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As mentioned that memory is not interleaved, so we will not assume parallel access in memory banks, hence, there is only one memory module .

Total time taken for a sequential access in MM

=> one clock cycle is required to send an address to main memory

four clock cycles to access a $32$-bit word (a single word) from main memory

+ Time required to access remaining $3$ words ( one clock cycle per word transfer )

=> $1 + 4 + 3$

=> $8$ clock cycles are needed to transfer it to the processor and hence will be transferred to cache parallely .

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