cache and main memory

Question

Assume the following performance characteristics on a cache read miss:

one clock cycle to send an address to main memory and four clock cycles to access a 32-bit word from main memory and transfer it to the processor and cache. What is the miss penalty if the cache line size is four words and a transfer is executed, with one clock cycle per word transfer?

What would be the answer if memory is not interleaved and word access is done sequentially from main memory?

Comments

for this Question please do not assume parallel access from main memory.

MM is not interleaved I have mentioned.

Answer 1

As mentioned that memory is not interleaved, so we will not assume parallel access in memory banks, hence, there is only one memory module .

Total time taken for a sequential access in MM

=> one clock cycle is required to send an address to main memory

+ four clock cycles to access a $32$-bit word (a single word) from main memory

+ Time required to access remaining $3$ words ( one clock cycle per word transfer )

=> $1 + 4 + 3$

=> $8$ clock cycles are needed to transfer it to the processor and hence will be transferred to cache parallely .

Comments

@kapil..remaining portion of the book example

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Its interleaving example. Do u want me to explain that ?

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I understand this an example parallel access. No need to explain as the question is already explained in the book.

The point is they have taken M as cache miss penalty.

• M = $38$ cycles when serial access
• M = $17$ cycles when parallel access 

In relation to serial access can you please explain a bit more on your approach of getting the penalty of 8 cycles. I understand that your idea of miss penalty includes everything (copy to cache + send to processes). OK fine !

Still elaborate your solution.