As mentioned that memory is not interleaved, so we will not assume parallel access in memory banks, hence, there is only one memory module .
Total time taken for a sequential access in MM
=> one clock cycle is required to send an address to main memory
+ four clock cycles to access a $32$-bit word (a single word) from main memory
+ Time required to access remaining $3$ words ( one clock cycle per word transfer )
=> $1 + 4 + 3$
=> $8$ clock cycles are needed to transfer it to the processor and hence will be transferred to cache parallely .