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Recent questions tagged write-through
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computer organization refrence book
System with the main memory access time 200ns and cache access time is 10ns.hit ratio for read req is 0.8 and 80% are hit for memory read,if write throug technique is used , what is average time consider both R and Write? my approch is $\frac{80}{100}$(0.8(10)+0.2(10+200) + $\frac{20}{100}$(max of (200,10)=200) 80 where i am wrong?
System with the main memory access time 200ns and cache access time is 10ns.hit ratio for read req is 0.8 and 80% are hit for memory read,if write throug technique is use...
jugnu1337
259
views
jugnu1337
asked
Jul 18, 2023
CO and Architecture
write-through
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0
votes
3
answers
2
Appllied Gate Test Series
A hierarchical memory system that uses cache memory has cache access time of 80 nanoseconds, main memory access time of 200 nanoseconds, 85% of memory requests are for read, hit ratio of 0.9 for read access and the write-through scheme is used. What will be the average access time of the system both for read and write requests ?
A hierarchical memory system that uses cache memory has cache access time of 80 nanoseconds, main memory access time of 200 nanoseconds, 85% of memory requests are for re...
Sagar475
1.1k
views
Sagar475
asked
Jan 16, 2022
CO and Architecture
co-and-architecture
cache-memory
write-through
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0
votes
1
answer
3
https://gateoverflow.in/14480/formula-write-back-write-through-access-time-parallel-serial
In this question can someone plz explain to me the write back part? Why are we taking write back time only for cache misses? Why not for hits? How to know when a block is going to be replaced and when to consider write back time.
In this question can someone plz explain to me the write back part? Why are we taking write back time only for cache misses? Why not for hits? How to know when a block i...
sushmita
776
views
sushmita
asked
Dec 12, 2018
CO and Architecture
cache-memory
co-and-architecture
write-through
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0
votes
0
answers
4
Stallings (write through)
Consider a cache with a line size of 32 bytes and a main memory that requires 30 ns to transfer a 4-byte word. For any line that is written at least once before being swapped out of the cache, what is the average number of times that the line must be written before being swapped out for a write-back cache to be more efficient that a write-through cache?
Consider a cache with a line size of 32 bytes and a main memory that requires 30 ns to transfer a 4-byte word. For any line that is written at least once before being swa...
Ajit J
839
views
Ajit J
asked
Dec 10, 2018
CO and Architecture
co-and-architecture
cache-memory
write-through
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0
votes
1
answer
5
homework
Main disadvantage of direct mapping is that cache his ratio decreases sharply it two or more frequently used blocks map on to same region. For two level memory hierarchy cache and main memory, WRITE THROUGH results in more write cycles to main emeory then WRITE BACK. is it true or false ? with reasons ? thank you in advance
Main disadvantage of direct mapping is that cache his ratio decreases sharply it two or more frequently used blocks map on to same region.For two level memory hierarchy c...
deepanshu sharma 3
494
views
deepanshu sharma 3
asked
Nov 17, 2018
CO and Architecture
co-and-architecture
cache-memory
write-through
true-false
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1
votes
2
answers
6
COA: Cache Accesss Time
Little confusion with these questions. What will be o/p for these two questions one with Write back and the other is Write through. 1.)A 128 word cache and main memory are divided into 8 word blocks. The access time of a cache ... average access time? What will be the default technique ( write-allocate and no write-allocate)followed for Hierarchal and Simultaneous access ?
Little confusion with these questions.What will be o/p for these two questions one with Write back and the other is Write through.1.)A 128 word cache and main memory are ...
Hemanth_13
822
views
Hemanth_13
asked
Nov 7, 2018
CO and Architecture
co-and-architecture
cache-memory
write-through
write-back
effective-memory-access
numerical-answers
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0
votes
1
answer
7
When to use word access time and when to use block access time in access time calculation.
Hello, I came across this question when practicing from a gate app. My question is here simultaneous access is used and hence we are transferring from cache to cpu if hit or main memory to ... is needed. Added the image of question. Thanks https://gateoverflow.in/?qa=blob&qa_blobid=13957411914537045045
Hello, I came across this question when practicing from a gate app. My question is here simultaneous access is used and hence we are transferring from cache to cpu if hit...
Chaitrasj
214
views
Chaitrasj
asked
Oct 4, 2018
CO and Architecture
co-and-architecture
cache-memory
effective-memory-access
write-through
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0
votes
0
answers
8
Hierarchy or simultaneous
Deepalitrapti
497
views
Deepalitrapti
asked
Sep 26, 2018
CO and Architecture
co-and-architecture
cache-memory
effective-memory-access
write-through
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0
votes
0
answers
9
CACHE SELF DOUBT 2
Balaji Jegan
184
views
Balaji Jegan
asked
Sep 10, 2018
CO and Architecture
co-and-architecture
cache-memory
write-through
numerical-answers
self-doubt
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2
votes
3
answers
10
Write Trough
Do we consider hierarchical model or simultaneous access model for write through ?
Do we consider hierarchical model or simultaneous access model for write through ?
pa-try
1.3k
views
pa-try
asked
Dec 14, 2017
CO and Architecture
cache-memory
co-and-architecture
write-through
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0
votes
2
answers
11
Doubt on Write through
Consider the following specifications: Hit ratio for read = 0.8, Hit ratio for write = 0.9 Block size =2 words, cache of 10 ns is 10 times faster than main memory On any miss entire block is moved from main memory to cache memory 20% references are for write operations What is avg access time with write through using 1) Write allocate 2) No write allocate
Consider the following specifications:Hit ratio for read = 0.8,Hit ratio for write = 0.9Block size =2 words,cache of 10 ns is 10 times faster than main memory On any miss...
Anjan
1.0k
views
Anjan
asked
Nov 26, 2017
CO and Architecture
co-and-architecture
cache-memory
write-through
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2
votes
1
answer
12
Computer organization
A system which has lot of crashes, data should be written to the disk using A. Write-through B. Wtite-back C. Both
A system which has lot of crashes, data should be written to the disk usingA. Write-throughB. Wtite-backC. Both
rishu_darkshadow
1.8k
views
rishu_darkshadow
asked
Nov 4, 2017
CO and Architecture
co-and-architecture
write-through
write-back
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–
9
votes
2
answers
13
wrie through updation in cache
Consider a system with cache access time 20 ns and main memory access time 140 ns. If 60% operations are read operations and hit ratio is 90%. What is the effective access time if write through updation technique is used? (a) 75.2 ns (b) 76.4 ns (c) 83.2 ns (d) 84.4 ns
Consider a system with cache access time 20 ns and main memory access time 140 ns. If 60% operations are read operations and hit ratio is 90%. What is the effective acces...
Sunil8860
4.0k
views
Sunil8860
asked
Aug 6, 2017
CO and Architecture
co-and-architecture
cache-memory
write-through
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2
votes
0
answers
14
CO: William Stalling: Write Through and Write Back, which is more efficient.
According to my calculation, the time required in write back is 240ns and for write through it should be 1920ns. Is it correct or not?
According to my calculation, the time required in write back is 240ns and for write through it should be 1920ns. Is it correct or not?
Shubhanshu
784
views
Shubhanshu
asked
Aug 5, 2017
CO and Architecture
co-and-architecture
cache-memory
write-through
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1
votes
1
answer
15
[COA] Cache write through in hierarchical design
For hierarchical access and write-through,The average write time is given by: 1. Twt=H×Tmemory+(1−H)×(Tcache+Tmemory) 2. Twt=Tmemory Which one to refer in question?Can we ignore Tcache and use the second one? Please clarify?
For hierarchical access and write-through,The average write time is given by: 1. Twt=H×Tmemory+(1−H)×(Tcache+Tmemory)2. Twt=TmemoryWhich one to refer in question?Can ...
rahul sharma 5
941
views
rahul sharma 5
asked
May 20, 2017
CO and Architecture
cache-memory
co-and-architecture
write-through
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5
votes
1
answer
16
True or false
$S_1$: When the write-through protocol used in the simultaneous access memory organization then the hit ratio for write request is 100%. $S_2$: Conflict and Inference misses can be reduced by double the associativity of a cache design. $S_3$: In ... are required in the direct, associative and set associative cache designs to replace the cache blocks. Which of the following is false?
$S_1$: When the write-through protocol used in the simultaneous access memory organization then the hit ratio for write request is 100%.$S_2$: Conflict and Inference miss...
Supremo
2.3k
views
Supremo
asked
Jan 30, 2017
CO and Architecture
cache-memory
write-through
write-back
direct-mapping
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–
1
votes
1
answer
17
MadeEasy Workbook [2017] Q33 - Efficiency of Cache using Write Through Scheme
Data: Hit Ratio for Read Op - 80% Hit Ratio for Write Op - 90% There are 30% updations. Cache Access time: 20ns [CMAT] MM Access Time - 100ns [MMAT] If there is a miss (either for read or write entire 2 block word block ... i.e. 11.9 Million Ops per sec Please tell me if it's right or wrong or how it will be solved.
Data:Hit Ratio for Read Op - 80%Hit Ratio for Write Op - 90%There are 30% updations.Cache Access time: 20ns [CMAT]MM Access Time - 100ns [MMAT]If there is a miss (either ...
Shailendra1993
1.2k
views
Shailendra1993
asked
Dec 11, 2016
CO and Architecture
cache-memory
write-through
co-and-architecture
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–
0
votes
0
answers
18
Cache+memory
I am not understanding how options are given because even when one miss will occur entire cache block will be accessed, so 128 B will be accessed.
I am not understanding how options are given because even when one miss will occur entire cache block will be accessed, so 128 B will be accessed.
Rahul Jain25
341
views
Rahul Jain25
asked
Dec 9, 2016
CO and Architecture
cache-memory
co-and-architecture
write-through
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–
0
votes
1
answer
19
Write through Updation
Here , in sol. they have obtained ans as : 0.35*(max(40,50)) + 0.65 *(40+50) = 76 Shouldn't the access times be not considered at all?
Here , in sol. they have obtained ans as :0.35*(max(40,50)) + 0.65 *(40+50) = 76Shouldn't the access times be not considered at all?
prasitamukherjee
515
views
prasitamukherjee
asked
Nov 14, 2016
CO and Architecture
write-through
cache-memory
co-and-architecture
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–
1
votes
1
answer
20
Write through Cache
i'm not getting ans
i'm not getting ans
prasitamukherjee
1.0k
views
prasitamukherjee
asked
Nov 13, 2016
CO and Architecture
cache-memory
write-through
co-and-architecture
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–
2
votes
0
answers
21
Cache updation policy doubt
https://gateoverflow.in/10668/64-word-cache-and-main-memory-is-divided-into-16-words-block https://gateoverflow.in/21189/gate-q-43_44?show=21189#q21189 In this two questions, I am not getting how to find TavgW . In the first link they ... to cache. Which means hierarchical access. Plz tell me what's the difference between those question and how to solve them.
https://gateoverflow.in/10668/64-word-cache-and-main-memory-is-divided-into-16-words-blockhttps://gateoverflow.in/21189/gate-q-43_44?show=21189#q21189In this two question...
Digvijaysingh Gautam
481
views
Digvijaysingh Gautam
asked
Oct 15, 2016
CO and Architecture
write-through
cache-memory
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–
1
votes
2
answers
22
MadeEasy Test Series: CO & Architecture - Cache Memory
Array A contains 256 elements of 4 bytes each. Its first element is stored at physical address 4,096. Array B contains 512 elements of 4 bytes each. Its first element is stored at physical address 8,192. Assume that only arrays A and B can ... many bytes will be written to memory if the cache has a write-through policy? a. 0 b 256 c 1024 d 2048
Array A contains 256 elements of 4 bytes each. Its first element is stored at physical address 4,096. Array B contains 512 elements of 4 bytes each. Its first element is ...
khushtak
596
views
khushtak
asked
Jan 18, 2016
CO and Architecture
made-easy-test-series
co-and-architecture
cache-memory
write-through
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–
1
votes
0
answers
23
write through
Sourabh Kumar
526
views
Sourabh Kumar
asked
Jan 16, 2016
CO and Architecture
write-through
+
–
13
votes
1
answer
24
Write Back and Write Through
A 64 word cache and main memory are divided into 16 word blocks. The main memory access time is 50 ns/word and the cache access time is 10 ns/word. Hit ratio for read operation is 80% and for the write operation is 90%. Whenever a cache miss happens, associated ... are modified, What is Tavg in write back policy? Ans for : 1) is 6.5 Million words/sec 2) is 176.4 ns
A 64 word cache and main memory are divided into 16 word blocks. The main memory access time is 50 ns/word and the cache access time is 10 ns/word. Hit ratio for read ope...
Mojo-Jojo
6.6k
views
Mojo-Jojo
asked
Jan 11, 2016
CO and Architecture
co-and-architecture
look-aside
cache-memory
write-through
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–
6
votes
2
answers
25
Write Through Cache Policy Questions - As per me answer should be 30, Given as 46 ns !
Consider a two level memory hierarchy. L1 (cache) has an accessing time of 10 ns and main memory has an accessing time of 20 ns. Writing or updating contents into their memory takes 20 ns and 30 ns for L1 and ... be 30, as in write Through Main Memory is updated no matter what ! Made Easy FLT 6- Practice Test 14
Consider a two level memory hierarchy. L1 (cache) has an accessing time of 10 ns and main memory has an accessing time of 20 ns. Writing or updating contents into their m...
Akash Kanase
4.4k
views
Akash Kanase
asked
Dec 1, 2015
CO and Architecture
write-through
cache-memory
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–
7
votes
2
answers
26
Gate q-43_44
Consider a cache memory hit ratios for read and write operations are 80% and 90% respectively. If there is a miss then 2 word block is to be through from main memory to cache. Consider 30% updations and the cache access time is 20ns/word and memory access time 100 ns/word. Q43 ... efficiency of cache using write back scheme?( in million words per sec) A.15.5 b. 16.5 c. 14.5 d. 13.5
Consider a cache memory hit ratios for read and write operations are 80% and 90% respectively. If there is a miss then 2 word block is to be through from main memory to c...
khushtak
6.6k
views
khushtak
asked
Oct 19, 2015
CO and Architecture
co-and-architecture
write-through
cache-memory
+
–
19
votes
2
answers
27
64 word cache and Main memory is divided into 16 words block.
64 word cache and main memory is divided into 16 words block.The access time of cache is 10ns/word and for main memory is 50ns/word. The hit ratio for read operation is .8 and write operation is.9. Whenever there is ... to cache for read and write operation. 40% reference is for write operation. Avg access time if write through is used.
64 word cache and main memory is divided into 16 words block.The access time of cache is 10ns/word and for main memory is 50ns/word. The hit ratio for read operation is ....
Ram Sharma1
6.9k
views
Ram Sharma1
asked
May 20, 2015
CO and Architecture
co-and-architecture
cache-memory
write-through
effective-memory-access
numerical-answers
+
–
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