0 votes 0 votes answer is 6 but I’m getting 5(delay of NOR gate+delay of 1st MUX+delay of 2nd MUX)=2+1.5+1.5=5 ns where is extra 1 ns delay coming from? Digital Logic usergate2016-1 digital-logic multiplexer + – aditi19 asked Nov 25, 2018 aditi19 1.6k views answer comment Share Follow See all 9 Comments See all 9 9 Comments reply kumar.dilip commented Nov 25, 2018 reply Follow Share What about inverter ?? you should also add the inverter(T). 0 votes 0 votes Hemanth_13 commented Nov 26, 2018 reply Follow Share But why @kumar.dilip can't they be done in parallel?? 0 votes 0 votes aditi19 commented Nov 26, 2018 reply Follow Share exactly. inverter should be working in parallel 0 votes 0 votes Hemanth_13 commented Nov 26, 2018 i edited by Hemanth_13 Nov 26, 2018 reply Follow Share Actually see the functionality of device @aditi19 at any given time only one nor gate is active so it will be 6 0 votes 0 votes arya_stark commented Nov 26, 2018 i edited by arya_stark Nov 26, 2018 reply Follow Share https://gateoverflow.in/232649/ace_subject_test_digitallogic2019 S0(MUX1) and S1(MUX2) are select lines connected via NOT GATE and based on their values we are selecting the input already given. The input has already been given in the multiplexers. These lines are just helpful in determining our input. You can in a way take them to do the work of selection and not the input.. In electronics, digital circuits and digital electronics, the propagation delay, or gate delay, is the length of time which starts when the input to a logic gate becomes stable and valid to change, to the time that the output of that logic gate is stable and valid to change. Here also there is no clock applied,otherwise it will result in a race condition. 0 votes 0 votes arya_stark commented Nov 26, 2018 reply Follow Share Ma'am please observe This " T " CASE1 : If T = 0 then it choose NOR gate in MUX1. For MUX2 T will become 1. So it choose MUX1's out put CASE 2 : If T = 1 then it choose Inverter gate in MUX1. For MUX2 T will become 0. So it choose NOR. @Hemanth_13 Correct me if i wrong. 0 votes 0 votes Hemanth_13 commented Nov 26, 2018 reply Follow Share When T=0 one NOR gate + 1MUX + 1 MUX=> 2+1.5+1.5==>5 When T=1 One inverter + One MUX + NOR + Another MUX = 1 + 1.5 + 2 + 1.5 ===>6 Note that inverter @ select lines is done at parallel. Hope this helps 0 votes 0 votes Shaik Masthan commented Nov 26, 2018 reply Follow Share it is MUX and note that the selecting lines are inverse to each other case 1 :- T=0 ===> i0 of Mux1 and i1 of Mux2 need to evaluate. at time k=0, P,Q,R,S and T are loaded ===> i0 of Mux1 available at k=2 (due to NOR gate) then MUX1 evaluate completes at k=2+1.5 = 3.5, output of MUX1 is used as i1 of Mux2 ===> at k=3.5+1.5(for MUX2 evaluation) = 5, MUX2 evaluation completes. case 2 :- T=1 ===> i1 of Mux1 and i0 of Mux2 need to evaluate. at time k=0, P,Q,R,S and T are loaded ===> i1 of Mux1 available at k=1 (due to NOT gate) then MUX1 evaluate completes at k=1+1.5 = 2.5, output of MUX1 is used as i0 of Mux2 ===> at k=2.5+2(for evaluating i0 of MUX2 due to NOR gate ) = 4.5, Now MUX2 evaluation completes at 4.5 + 1.5(for evaluating MUX2 ) = 6 0 votes 0 votes Rajesh Panwar commented Jan 5, 2019 reply Follow Share why at any given time only one nor gate is active ? 0 votes 0 votes Please log in or register to add a comment.