Madeeasy-Test-series

Question

consider a RISC processor with an ideal CPI, where 25% of total instructions are Load and Store instructions. The time to access the main memory is 100 clock cycles and accessing of the cache memory required 2 clock cycles. if the cache miss rate is 2%, then the effective CPI for the system with the cache is __.{up to 2 decimal}.

Comments

3.5?

---

answer is 5 (as given ).

---

Have they given the solution?

---

I think answer depends on the clock cycles an instruction takes. If a load & store instruction takes 2

clock cycles and all other instructions take 1 clock cycle, then you'll get CPI = 5.

---

i am not getting solution-

---

@Prateek Raghuvanshi

As I said earlier that if load and store take 2 cycle, then my solution:

let h = cache hit rate, Tc = cycles for cache access, Tm = cycles for MM access



avg CPI for L&S: $h*Tc*2 + (1-h)*(Tc+Tm)*2$

                            $0.98*2*2 + 0.02*(100+2)*2$ $= 8$


avg CPI for other instructions: $h*Tc + (1-h)*(Tc+Tm)$

                            $0.98*2 + 0.02*(100+2)$ $= 4$

avg CPI $=$ 0.25*avg CPI for load and store + 0.75*avg CPI for other instructions
            $= 0.25 * 8 + 0.75*4 = 5$



 

---

@ neeraj33negi i am not getting why are you taking 2 cycle ,given answer may be wrong ,i just want to know what is question is trying to say ? and what will be possible solution for it.

---

I am just assuming 2 cycles for load and store, actually the question must mention how many clocks each type of instruction takes. I just took 2 because it is the only option which gives 5 as answer but the method is correct. https://en.wikipedia.org/wiki/Cycles_per_instruction

check example 1 in the link

---

There is nothing given like that  ,then we can't assume anything for getting answer.

---

I think we can do it this way:

Memory Stall Cycles = IC * (MemoryAccess/Instruction) * Miss Rate * Miss Time = 1.25*0.02*100
Memory Hit Cycles = IC * (Memory Access / Instruction) * Hit Rate * Hit Time = 1.25*0.98*2

Memory Access / Instruction will be 1.25 (1 + 0.25) since 25 % of the instructions are Load/Store. Here one represents the instruction access and 0.25 represents the data access.

So total number of cycles will be the sum of both, which comes to IC*4.95.

So average CPI will be memory cycles/IC, giving the answer as 4.95.

---

There was a somewhat similar question here. Look at how they've calculated MemAcc/Instruction.

Answer 1

 

1. Ideal CPI for non-load/store instructions:

Since the processor has an ideal CPI, we can assume that all non-load/store instructions take 1 cycle.

2. CPI for load/store instructions:

Cache hit: 2 cycles (accessing the cache)

Cache miss: 100 cycles (accessing main memory)

3. Effective CPI for load/store instructions:

 

25% of instructions are load/store

2% of load/store instructions result in cache misses

Effective CPI for load/store = 0.25 * (0.02 * 100 + 0.98 * 2) = 0.505

4. Overall effective CPI:

 

75% of instructions are non-load/store (CPI = 1)

25% of instructions are load/store (CPI = 0.505)

Overall effective CPI = 0.75 * 1 + 0.25 * 0.505 = 0.8763