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Consider a computer with a $4$-ways set-associative mapped cache of the following character­istics: a total of $1\;\text{MB}$ of main memory, a word size of $1\;\text{byte}$, a block size of $128$ words and a cache size of $8\;\text{KB}$.

While accessing the memory location $\text{0C795H}$ by the CPU, the contents of the TAG field of the corresponding cache line is:

  1. $000011000$
  2. $110001111$
  3. $00011000$
  4. $110010101$
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4 Answers

Best answer
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As shown in https://gateoverflow.in/3403/gate2008-it_80

We have $16$ sets in cache and correspondingly $16$ regions in physical memory to which each set is mapped.
Now, $\text{WORD}$ bit size is $7$ as we need $7$ bits to address $128$ possible words in a cache block.
So, the lowest $7$ bits of $\text{0C795H}$ will be used for this giving us the remaining bits as $\text{0000 1100 0111 1}$

Of these bits, the lower $4$ are used for addressing the $16$ possible sets, giving us the tag bits$: 0000\, 1100\, 0$ in (A) choice.

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20 bit physical address will be divided into

9-tag, 4-set 7-word

so answer will be A
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TAG will take= 9 bits


SET will need 4 bits and


WORD will need 7 bits of the cache memory location


(using the above conclusion as derived in previous question)
The memory location 0C795H can be written as 0000 1100 0111 1001 0101


Thus TAG= 9 bits = 0000 1100 0


SET =4 bits =111 1


WORD = 7 bits =001 0101


Therefore, the matching option is option A.

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