GATE IT 2008 | Question: 81

Question

Consider a computer with a $4$-ways set-associative mapped cache of the following character­istics: a total of $1\;\text{MB}$ of main memory, a word size of $1\;\text{byte}$, a block size of $128$ words and a cache size of $8\;\text{KB}$.

While accessing the memory location $\text{0C795H}$ by the CPU, the contents of the TAG field of the corresponding cache line is:

• A. $000011000$
• B. $110001111$
• C. $00011000$
• D. $110010101$

Comments

one quick observation lets suppose we are not finding the #of tag bits bcz in the given options eiither it is $8$ or $9$ so any wayu'll take MSb 4 bits of $0's$ so straightforward ans is $A$ no need to calculate here :)

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To answer this question we don't need any of the information given

if we check the most significant bits with the options will be sufficient

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$Tag\ Bits=log_2(MM_{size})-log_2(cache_{size})+2\ bits\ (\because 4-way\ set\ associative)=9\ bits$
$9\ bits\ from\ MSB=0C0=0000\ 1100\ 0\ i.e\ (a)$

Answer 1

As shown in https://gateoverflow.in/3403/gate2008-it_80

We have $16$ sets in cache and correspondingly $16$ regions in physical memory to which each set is mapped.
Now, $\text{WORD}$ bit size is $7$ as we need $7$ bits to address $128$ possible words in a cache block.
So, the lowest $7$ bits of $\text{0C795H}$ will be used for this giving us the remaining bits as $\text{0000 1100 0111 1}$

Of these bits, the lower $4$ are used for addressing the $16$ possible sets, giving us the tag bits$: 0000\, 1100\, 0$ in (A) choice.

Comments

how this ??So, the lowest 7 bits of 0C795H will be used for this giving us the remaining bits as
0000 1100 0111 1 bcz lower of 0C795H is 0111 1001 0101 

shd consider msb bit for tag y considering lsb???? & as here 0000 1100 0111 1 it seems msb then y 1 y not 0101 ????
 

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We have 7 offset bits and 4 index bits. So, all other bits form the tag bits.

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@Arjun sir, Here cache is physically addressed.But in case of any ambiguity by default which type of case we assume Virtually cache of physically cache?

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if nothing is given, cache is generally physically addressed cache

Answer 2

..…..………………………………………………….

Answer 3

20 bit physical address will be divided into

9-tag, 4-set 7-word

so answer will be A

Comments

@ Monisha 

by using only these info. how u concluded option A is right ans ????/

Answer 4

TAG will take= 9 bits

SET will need 4 bits and

WORD will need 7 bits of the cache memory location

(using the above conclusion as derived in previous question)
The memory location 0C795H can be written as 0000 1100 0111 1001 0101

Thus TAG= 9 bits = 0000 1100 0

SET =4 bits =111 1

WORD = 7 bits =001 0101

Therefore, the matching option is option A.