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GATE IT 2006 | Question: 78

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A pipelined processor uses a $4-$stage instruction pipeline with the following stages: Instruction fetch (IF), Instruction decode (ID), Execute (EX) and Writeback (WB). The arithmetic operations as well as the load and store operations are carried out in the EX stage. The sequence of instructions corresponding to the statement $X = (S - R * (P + Q))/T$ is given below. The values of variables $P, Q, R, S$ and $T$ are available in the registers $R0, R1, R2, R3$ and $R4$ respectively, before the execution of the instruction sequence.
$$\begin{array}{ll} \text{ADD} & \text{R5, R0, R1} && \text{; R5 ← R0 + R1} \\  \text{MUL} & \text{R6, R2, R5} && \text{; R6 ← R2 * R5} \\   \text{SUB} & \text{R5, R3, R6} && \text{; R5 ← R3 - R6} \\  \text{DIV} & \text{R6, R5, R4} && \text{; R6 ← R5/R4} \\ \text{STORE} & \text{R6, X} && \text{; X  ← R6} \\ \end{array}$$
The number of Read-After-Write (RAW) dependencies, Write-After-Read( WAR) dependencies, and Write-After-Write (WAW) dependencies in the sequence of instructions are, respectively,

  1. $2, 2, 4$
  2. $3, 2, 3$
  3. $4, 2, 2$
  4. $3, 3, 2$
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2 Answers

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53 votes

(C) is the correct option for this question:

RAW

  1. I1 - I2 (R5)
  2. I2 - I3 (R6)
  3. I3 - I4 (R5)
  4. I4 - I5 (R6)


WAR 

  1. I2 - I3 (R5)
  2. I3 - I4 (R6)


WAW

  1. I1 - I3 (R5)
  2. I2 - I4 (R6)
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