Maximum clock frequency for the circuit

Question

In the following digital circuit shown above, the worst case delay is of 30 nsec and the AND gate has delay of 10 nsec. The maximum clock frequency of the circuit to operate is _ MHz.

I calculated as follows : $T_{Clk} \geq T_{flip-flop} + T_{AND gate}$

So, $\frac{1}{f_{Clk}} \leq \frac{1}{40}$

Here, we will just add the flip-flop delay once? The solution gives the frequency as 14.2 MHz, adding the delay due to flip-flop twice. Why?

Answer 1

In synchronous circuits, we have,  $T_{propagation-delay} = T_{flipflops} + T_{combinational}$  and In asynchronous circuits , We have : $T_{propagation-delay} = n*T_{flipflops} + T_{combinational}$

But in the question above, two FF's  are given same clock (so these will respond to clock at same time) and the remaining Flip Flop is given the output of other Flip Flop ( so it will wait for output of first flip flop).

Here, $T_{propagation-delay} = 2*T_{flipflops} + T_{combinational}$ and $T_{clock}$  $\geq$  $T_{propagtion-delay}$.

$\frac{1}{freq_{clock}} \geq 2*30ns + 10ns$
$freq_{clock} \leq \frac{1000*10^{6}}{70}$
thus, $freq_{clock} \leq 14.2857 MHz$

Comments

The leftmost FF has direct signal fed to J-input and clock. The output of leftmost FF is given to clock of middle FF. The output of the middle FF is given to the input of the rightmost FF. So in any case the valid output at Q3 will be available after time delay of all 3 FFs (which we need to consider / add up separately) and the delay of AND gate.
So I feel it should be

$\frac{1}{freq_{clock}}>=3\times 30 + 10$

Am I correct?

---

Here FF1 and FF3 both work parallely, but output of FF1 is given as clock to FF2, so FF2 can only work when output of FF1 is available, that's why delay = 2*30 + delay of and gate

---

So should we be only looking at just the clock inputs, not J-inputs? Because $J_2 = Q_0.Q_1$ (indexing them 0 to 2 starting from left).

$Q_1$ is valid after propagation delay of FF0 + FF1, thats 60 ns. So $J_2$ is valid only after 60ns as $J_2 = Q_0.Q_1$. Also immediately after 60ns, $Q_2$ will not be valid, as propagation delay of FF2 should also be considered. So it becomes 90ns + propagation delay of AND gate. So thats total 90+10 = 100 ns

Or should we completely ignore the fact that $J_2 = Q_0.Q_1$  and only clock inputs matter?

---

Yes, Only clock matters.

---

I guess this is wrong.
Putting one FF in between which operates in async mode makes last FF operate in async mode.
Let me explain.

Forget last flip flop. Consider delay till AND gate only.
It will be 30*2+10 = 70ns

Now add last FF back. This FF will become active after 70ns only.
Correct me if am wrong.

If you look at the output of FF2 at the end of 70ns, it will be unchanged. But after another 30ns, it will change.

Even the clock is shared between FF0 and FF2, FF2 starts operating only after FF0 , FF1 and AND gate have finished their work and hence total delay will be 30*2+10 + 30 = 100 ns