GATE IT 2004 | Question: 46

Question

If we use internal data forwarding to speed up the performance of a CPU (R1, R2 and R3 are registers and M[100] is a memory reference), then the sequence of operations

R1 → M[100]
M[100] → R2
M[100] → R3

can be replaced by

• A. R1 → R3
  R2 → M[100]
• B. M[100] → R2
  R1 → R2
  R1 → R3
• C. R1 → M[100]
  R2 → R3
• D. R1 → R2
  R1 → R3
  R1 → M[100]

Comments

i have a doubt In case of PIPE-LINING  we use internal  DATA FORWARDING to MINIMIZE data hazards or to get better performance.

---

I think you are confused with the meaning of data hazards. Because if the data hazards are minimized .means the number of stalls are minimized, ultimately improves the performance. so all the terms are pointing indirectly to each other.

---

@ saurabh

why do u think

" internal  DATA FORWARDING cannot MINIMIZE data hazards "

Answer 1

Data forwarding means if CPU writes to a memory location and subsequently reads from the same memory location, the second instruction can fetch the value directly from the register used to do the write than waiting for the memory. So, this increases the performance.

Here, choices A, B and C doesn't really make any sense as the data was in R1 and it must be moved to R2, R3 and M[100]. So, (D) is the answer.

Comments

Arjun SIR CAN WE DO IT SIMPLY BY TAKING RANDOM VALUES AND SEE WHICH GIVES THE SAME OUTPUT WITHOUT NOTICING ABOUT DATA FORWARDING CONCEPT?

---

Just want to confirm that, if we have, for example an instruction, which is moving contents of a Register to a Memory location, then the micro-operation $R1 \rightarrow M[address]$ will take place in which stage? Is it EX or WB stage?. I am confused.

---

@ayushsomani

if we say that the instruction, which is moving contents of a Register to a Memory location is STORE instruction , then for store instructions the effective address calculation(address of memory location where we want to store register data) is done in EX stage. And the contents of register are stored at memory location in MEM or MA stage and no action in WB stage.

So micro-operation R1→M[address] is done in MEM stage(4^th stage among 5 stages).

---

@swami_9 .. nah nah , in store and load operations , execute stage do nothing.. finding addresess of source and destination will be done during Operand fetch phase. Using mar we will contact with memory that's it...

Answer 2

Option A
here content of $R2$ is written to $M[100]$, but $R2$ doesn't have content of $R1$, so not even correct

Option B
here content of $R1's$ content is stored into $R2$ and $R3$, but $M[100]$ doesn't have content of $R1$

Option C
here $R2's$ content is written to $R3$, but $R2$ don't have content of $R1$ in the first place

Option D : Answer
The CPU avoids waiting for the slow memory $M[100]$ for the register operations. $R2$ and $R3$ get their data instantly from $R1$ inside the CPU, drastically speeding up the sequence and it is the only functionaly correct option
 

Answer 3

Correct Answer: Option D

option a:  

R1 → R3
R2 → M[100] 

here only R3 have content of R1, but R2 and M[100] doesn't

option b: 

M[100] → R2
R1 → R2
R1 → R3

 here R2 and R3 have the content of R1 but M[100] doesn't

option c:

R1 → M[100]
R2 → R3

here only M[100] contains the value of R1 whereas R2 and R3 don't

option d:

R1 → R2
R1 → R3
R1 → M[100]

here all R2,R3 and M[100] contains the content of R1

therefore correct option is d