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NIELIT 2022 April Scientist B | Section B | Question: 99

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A $5$ stage pipelined $\text{CPU}$ has the following sequence of stages:

  • $\text{IF}$ – instruction fetch from instruction memory
  • $\text{RD}$ – Instruction decode and register read
  • $\text{EX}$ – Execute: $\text{ALU}$ operation for data and address computation
  • $\text{MA}$ – Data memory access – for write access, the register read at $\text{RD}$ state is used.
  • $\text{WB}$ – Register write back

Consider the following sequence of instructions:

  • $\text{I1 : L  R0}, loc 1; \text{R0} <= \text{M}[loc1]$
  • $\text{I2 : A R0, R0;} \text{R0} <= \text{R0} +\text{R0}$
  • $\text{I3 : S R2, R0;} \text{R2} <= \text{R2} – \text{R0}$

Let each stage take one clock cycle.

What is the number of clock cycles taken to complete the above sequence of instructions starting from the fetch of $I_1$?

  1. $8$
  2. $10$
  3. $12$
  4. $15$

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