A CPU has a cache of 64 bytes. The main memory has K-banks, each bank can store C-bytes of data. The consecutive ‘C’ byte chunks are mapped to consecutive banks with wrap around manner , all K-banks can accessed in parallel. However the two accesses for the same bank have to be serialised (one after the other). Le ‘k’ equal to 24 and ‘c’ equal to 2. Each iteration requires decoding the bank numbers to be accessed in parallel and this takes (k/2)ns. Latency of each addressing bank is 80ns. How much time is required to transfer initial block of cache,
