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The below question is from Made Easy Test series

The diagram shows single bus detached DMA configuration for a system. How many times system bus is used for single data transfer using DMA(Consider only data transfer, not command or status transfer) 

 

  1. 1
  2. 2
  3. 3
  4. 0

Here answer according to their solution is option B.

Reason: One access of system bus for data transfer from i/o to DMA and other for data transfer from DMA to memory.

 

My Doubt: In DMA their is direct data transfer from i/o to memory so system bus is accessed only once.

Is this correct?

 

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Thanks ! so it is in the DMA controller. got it.

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@Shubham Sharma 2 according to the pdf you mentioned the data first gets stored in the disk controller(i.e data preparation) so for this 1 bus access. 

And then from disk controller it is transferred to memory (i.e data transfer )so 1 bus access. 

So total 2 bus access.

But if we consider this then bus is busy for data preparation as well as data transfer but this shouldn't happen as bus should be busy only during data transfer time.

Please correct me if I am wrong.

 

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@Chaitanya Kale Please read all the details mentioned in the answer, particularly the reference to William Stallings. I hope it will clear your doubt.

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1 Answer

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The DMA mechanism can be configured in a variety of ways, which are:

  • Single-bus detached DMA.
  • Single-bus integrated DMA-I/O
  • I/O bus

In Question – Single bus detached DMA is mentioned and in this two “system bus” cycles are needed.

@Chaitanya Kale, When the data is about to be transferred, the DMA controller gets access to the system bus from the CPU.

But if we consider this then bus is busy for data preparation as well as data transfer but this shouldn't happen as bus should be busy only during data transfer time.

When the device has a lot of data to be transferred, we will surely need some buffer to store the access amount, so the natural question will be how will that data reach the buffer. it has to be through the bus, right? 

1st ref. → DMA configuration

2nd ref. → One- And Two-Step DMA Transfers (Page no. 2)

3rd ref. → Computer Organization and Architecture Designing for Performance, William Stallings, 10th ed, Chap-7, Page no. 250-251.

Directly Quoting from Stallings below:

“The DMA mechanism can be configured in a variety of ways. Some possibilities are shown in Figure 7.14. In the first example, all modules share the same system bus.

The DMA module, acting as a surrogate processor, uses programmed I/O to exchange data between memory and an I/O module through the DMA module. This configuration, while it may be inexpensive, is clearly inefficient. As with processor-
controlled programmed I/O, each transfer of a word consumes two bus cycles.”

Another ref. → Configurations of DMA

Whereas in “single-bus, integrated DMA-I/O, and I/O bus”, only 1 system bus cycle is needed. Below is another quote from William Stallings which confirms the same.

In both of these cases (Figures 7.14b and c), the system bus that the DMA module shares with the processor and memory is used by the DMA module only to exchange data with memory. The exchange of data between the DMA and I/O modules takes place off the system bus.

 

So the answer is Option B.

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