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+75 votes

We want to design a synchronous counter that counts the sequence $0-1-0-2-0-3$ and then repeats. The minimum number of $\text{J-K}$ flip-flops required to implement this counter is _____________.

in Digital Logic by Loyal (7.2k points)
retagged by | 17.9k views

2no of flip flops needed >= mod of the circuit 

in this question mod of counter is 6 and let no of flip flops be X;

2>= 6

answer = 3 

no of states is 6, but out of those 3 should correspond to 0..
do u have any link that supports the theory behind ur answer ?? coz i just followed standard procedure !!
no i dont have any link , but i m sure.. lets see in the official key.
And its not a standard question, so you cant  follow standard procedure..
for that type ques ans is not clear .someone plz explain in detail ....
we need four JK flipflops..
0->1->0->2->0->3 They are in non determensitic manner


There are 6 states and 3 of them correspond to same state.. ie non-deterministic
to differentiate between 0,1,2,3 we need 2 bits.

to differentiate between 3 0's we need 2 bits..
So total 4 bits=4 FF

@Shaik Masthan

plz explain this question!

read the best answer, i can't explain more than that answer !

@ why 3 can not be the correct answer?

in the official key, they provided 3 or 4

@Shaik Masthan

The extra bits which we are putting to eliminate duplicate can be of any order ?


@Shaik Masthan

If the sequence was 0 - 1 - 0 - 2 - 3 .... then we would require 3 FFs right????


Please update this. The answer is 3 or 4 as per the official key.

12 Answers

+100 votes
Best answer

We need four JK flipflops.
$0\to 1\to0\to2\to0\to3$

There are $6$ states and $3$ of them correspond to same states.
To differentiate between $0,1,2,3$ we need $2$ bits.
To differentiate between $3$ $0's$ we need another $2$ bits.
So, total $4-bits\to 4 FFs$

whether using extra combinational logic for output is allowed in a counter?
Page No. 10/11

Now, if you see the counters, now a counter we can define in this way the counter is a degenerate finite state machine, where the state is the only output. So, there is no other primary output from this machine, so the counter is defined like that.


Page No. 3

Counter you know what counter it is, that’s what we want we count the output of counter what is the particular count what is the current count that is the output of a count so no external output. The counter is a case of a state machine in which there are no external inputs, no external outputs. 

Page No. 10

At 35:30 www[dot]youtube[dot]com/watch?v=MiuMYEn3dpg

Here In Counter, we cannot use external variable, that purpose will be served by FF's only
We have four distinct states $0,1,2,3$ so, $2 FF$ for them for $3$ $0's$ to distinguish we need $2$ more $FF's$

$4 FF$ required.

by Loyal (9.7k points)
edited by
Can u plz explain how we actually eliminate rest of the states like 0010 , 0101 , and directly jump from 0001 to 0100 .
@abhilashpaniker29 wont it be similar to
Yes, i agree with you.. its a similar question.. the logic used is also almost the same.
In the official gate answer key: 3 is the correct answer.
3 FF correct Ans.
i agree with this answer that 4 flip flops are required as we need 3 different binary number which can give us 00 in end to differenciate the different state,

see it like this you care going 00->01-->00->10->00->03 here you will have thre transition from 00 to 01,10, & 11 and to differenciate between these 3 states you need to have diffrent code for 00 which can be 0000,0100,1000 you have to use atleast 4 digits so your final transition will become like this 0000->0001->0100->0010->1000->0011  if we take last two digits as output we will get our sequence and  our answer
The extra bits which we are putting to eliminate duplicate can be of any order ?


Can someone please check this pdf link as it is not working.



Can someone please check this pdf link as it is not working.


links are not working
+18 votes

I am using two AND gates and a NOT gate along with 3 flip flops.

there are 6 unique states. lets assume there is a  synchronous counter the generates below sequence:


Let output of 3 flip flops be S1, S2 , S3. Take them through below circuit  

S1 S2  S3  A  B  
1 0 0 1 0 0
0 0 1 0 0 1
1 0 1 1 0 0
0 1 0 0 1 0
1 1 0 1 0 0
0 1 1 0 1 1

if we take B C as final output we can generate 0->1->0->2->0->3. 

So I think it is possible with 3 flip flops.

Requesting comments.

by (115 points)
edited by

The problem in your approach is the synchronous counter(i.e JK FF's) is not counting the required sequence..
In a synchronous counter.. the count is considered as being the state of the flipflops, and count sequence is the change of these flip flop states .. so the JK FF's must go through the states 0->1->0->2->0->3
according to standard defintion..
so according to your approach.. the counts are.. 100->001->101...etc.. which are the states of the flipflops..

You can also see here, the steps for designing a synchronous counter

You yourself have written..
"lets assume there is a  synchronous counter the generates below sequence:"

and the question says.. 
We want to design a synchronous counter that counts the sequence 0-1-0-2-0-3
so i hope you are understanding what I am talking about..


This is a combinational circuit, right?
@Praveen Saini yes, My idea is to attach the combinational circuit to outputs of synchronous counter(with 3 flip flops) and take final outputs B C after each clock to get the required sequence
In any sequential logic circuit, Next state should  depend on present state ( in/excluding input variables).
Also,as i said above.. the count in a counter is defined based on the current state of the Flipflops.. if the question had mentioned.. to design a sequential circuit, may be your approach would have been right.. But it is explicitly mentioned in the question - a synchronous counter which counts the given count sequence.. so the JK flipflops have to go through the given sequence..

@Praveen Saini

Sure, and attaching this circuit to synchronous counter does not change that.

The above circuit as a whole is still a sequential circuit. Isn't it?


I am not sure about the standard definition of states of synchronous counter that you mentioned.

In the state sequence 100->001->101->010->110->011->100 all states are unique. so we can obviously design a synchronous counter that produces that state sequence(correct me if wrong). So I said to just assume. Anyhow I tried to design it below until excitation table step.  

Q1 Q2 Q3 Q1+ Q2+ Q3+ J1 K1 J2 K2 J3 K3
1 0 0 0 0 1 X 1 0 X 1 X
0 0 1 1 0 1 1 X 0 X X 0
1 0 1 0 1 0 X 1 1 X X 1
0 1 0 1 1 0 1 X X 0 0 X
1 1 0 0 1 1 X 1 X 0 1 X
0 1 1 1 0 0 1 X X 1 0 X

From above table we can get equations for J1 K1, J2 K2, J3 K3 using K-map and then connect them to get the synchronous counter circuit that generates 100->001->101->010->110->011->100 sequence.

Note: Q1, Q2, Q3 here are same as S1, S2, S3 used in initial answer.

Comments are welcome.


See, the circuit you have drawn is not at all wrong.. i am not commenting anything on that.. I am just trying to draw light on the approach you have taken..
there is a certain difference between a sequential circuit and a synchronous counter
synchronous counter is a sequential circuitbut not all sequential circuits are synchronous counters..
Thats what I am trying to point out..
The exact question is 
"We want to design a synchronous counter that counts the sequence 0102030−1−0−2−0−3 and then repeats."

So, the counter needs to count the sequence, getting my point? The counter itself needs to go through the states 0-1-0-2-0-3..

Also, if you disagree, with what I am saying, can you please give a proper reference of designing a synchronous counter using gated outputs??

I have tried referring Morris Mano, Charles Roth and R P Jain.. In all the three, the count in a synchronous or rather any kind of counter(ripple,johnson,etc) is always taken as the state of the flip flops.. thats why I am asking you for a standard reference for your approach..

I agreed with your logic.

Defintion of Counter.. from Charles Roth, Sixth edition..

"A counter is usually constructed from two or more flip-flops which change states in a prescribed sequence when input pulses are received."

From Morris Mano, Fourth edition..

"A Counter is essentially a register that goes through a predetermined sequence of binary
. "

Register is nothing but a group of the above two definitions are identical..

@Praveen Sir, is the approach right? for a synchronous counter?

for $Q_1Q_2Q_3$,  $100\rightarrow001\rightarrow101\rightarrow010\rightarrow110\rightarrow011$

here sequence given by $2Q_1'Q_2 +Q_1'Q_3$

if we can explicitly define it as here 

@Praveen so ans could be 3?
Yes. [ if we can use combination of state values to get sequence]

A counter is simply an ordered interconnection of many flip flops. The ‘state’ of a counter is defined simply as the ordered sequence of the states of the respective outputs of the individual flip flops that constitute it. To interconnect them, the inputs of the next flip flop are derived as a combination of other signals available in the circuit, using the gates. For a certain specified sequence of counter states, we need to manipulate the inputs of the individual flip flops in order to force them to make the desired transitions at specific times.


Lec 23 - Digital Systems Design by Prof.D.Roychoudhury, Department of Computer Science and Engineering,IIT Kharagpur

Watch from 26:45... 
Or you can go through the transcribed text here

I am attaching a part from the pdf..


it will be 4 FF only.

we can't take any equation to represent the sequence its only binary states of FF's and decimal representation of them.
how did u make the combinational circuit, just by logic or any standard approach?
+7 votes
IISC Answered it as either 3 or 4 . Both are correct . As seen , 2 bits are required to differentiate 3 Zeros hence 4 bits = 4FF

Also , someone may think it as 6 states and hence 2^3 = 8 >=6 Hence 3 is also correct .

Please note that these questions are repeatedly getting asked . We have to understand that only distinct states can be designed since we dont have dont care input in excitaion table. and hence we should not get confused. First make the states dinsinct with minimum bits. Similar question was asked in GATE 2015 . Please check .
by (325 points)
Shouldn't the answer be 3 then? Since they have asked for minimum number of JK FF required.
+3 votes
2 flip flops are required
by (121 points)
You are right there are only 4 states that is (0,1,2,3) it can be achieved using 2 JK flip flop and some gates.
+2 votes
both 3 and 4 are correct in the official key
by (173 points)
reshown by
Actually only one can be correct.. :P
IISC people are clever.. they just increased the error allowed in the answer - 3.0 to 4.0 :)
+2 votes

Both 3 and 4 were given the correct answer to this question in GATE this year

by Active (4.5k points)
+2 votes

Can we think like this ?

First we build a circuit for the sequence ; 0 - 1 - 4 - 6 - 8 - 11

To build this we need 4 FF, and after doing this, just connect $Q_1$ and $Q_0$ terminals to the decoder.

by Veteran (57.2k points)
What is advantage of it?
Can we just ignore the two most significant bit and take only the least 2 significant bit. No need of decoder. Can we ?
+1 vote

2no of flip flops needed >= mod of the circuit 

in this question mod of counter is 6 and let no of flip flops be X;

2>= 6

answer = 3 

by Junior (701 points)
Answer is either 3 or 4 as per IISC.But i think this approach is right also.

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