GATE CSE 2023 | Question: 33

Question

Consider a sequential digital circuit consisting of $\mathrm{T}$ flip-flops and $\mathrm{D}$ flip-flops as shown in the figure. $\text{CLKIN}$ is the clock input to the circuit. At the beginning, $\text{Q1, Q2}$ and $\text{Q3}$ have values $0,1$ and $1,$ respectively.

Which one of the given values of $\text{(Q1, Q2, Q3)}$ can $\text{NEVER}$ be obtained with this digital circuit?

• A. $(0,0,1)$
• B. $(1,0,0)$
• C. $(1,0,1)$
• D. $(1,1,1)$

Comments

@Sachi Mathur

D- flipflop doesn't work on positive edge triggered.

Why?

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Check this answer 

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Answer 1

From the given $3$ state counter made from $T$ flipflops and $D$ flipflops, the next input sequence are as follows:

• $T_1=\overline Q_3$
• $D_2=Q_1$
• $T_3=Q_2$

Initial State			Current input			Next State
$Q_1$	$Q_2$	$Q_3$	$T_1$	$D_2$	$T_3$	$Q_1^+$	$Q_2^+$	$Q_3^+$
0	1	1	0	0	1	0	0	0
0	0	0	1	0	0	1	0	0
1	0	0	1	1	0	0	1	0
0	1	0	1	0	1	1	0	1
1	0	1	0	1	0	1	1	1
1	1	1	0	1	1	1	1	0
1	1	0	1	1	1	0	1	1

we can see from the above table given counter count sequence like $011\rightarrow 000\rightarrow 100\rightarrow 010\rightarrow 101\rightarrow 111\rightarrow 110$. The state $001$ is missing.

Option (A) is correct.

Comments

By default if not given the sequence of state like Q1, Q2, Q3 then which should be LSB and which will be MSB?

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 Haris_md The very first time a clock pulse is applied to a specific flip-flop, it corresponds to the least significant bit (LSB). a particular flip-flop is LSB.

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here,

 T1= Q3'

D=Q1

T2= Q2

Assume first T flip-flop as T1 , D dlip-flop as D and second T flip-flop as T2

 

@Hira Thakur sir can you please rectify this !!

Answer 2

  We can solve these in 2 ways 

1st is full analysis of the given seq ckt

2nd one is :

 

so we don't get 001 if start state is 011 so option (a) is correct

Comments

the best explanation, thank you

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@Ahalya jadda Thanks alot but my question is in D and T2 shouldn't we fill D=Q1+ and for T2=Q2+ which is D or Q1+ ??

 

Answer 3

Here is the solution :