GATE CSE 2023 | Question: 11

Question

The output of a $2$-input multiplexer is connected back to one of its inputs as shown in the figure.

Match the functional equivalence of this circuit to one of the following options.

• A. $\text{D}$ Flip-flop
• B. $\text{D}$ Latch
• C. Half-adder
• D. Demultiplexer

Comments

@pranavbhosle_ so why this is a latch not a flip flop?

 

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Because this is just 1 latch and we need 2 for it to be a flip flop !?

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https://gemini.google.com/share/8adafe251acd

Answer 1

Here, input “0” is considered as $I_0$ and input “1” is considered as $I_1$ and output Q is considered as Y for the given MUX.

 

As we can see in the given figure that $I_0 = Y,$ $I_0$ is storing the previous state of output $Y.$

Now, the basic function of $D$ Latch is:

$1)$ When Enable(E) = $0,$ Output state has the same its previous state, we call it as Memory State or you can say informally as $Q_{n+1} = Q_n$

$2)$ When Enable(E) = $1,$ Output variable = Input variable

Now, here, make the setting as: 

Input: $I_1$ and Enable(E)= $S$

Now, As we have already seen that $I_0$ is storing the previous state of output. So, Say, previous state of output is $Y_{old}$ and Next state of output is $Y_{new}$

Now, According to the equation of $2 \times 1$ MUX i.e. $Y= \overline{S}I_0 + S I_1$

Since, $I_0 =Y_{old}$

Hence, we have

$Y_{new} = \overline{S}Y_{old} + S I_1$

Now,

$1)$ Make Enable(E)= $S = 0$, we get,

$Y_{new} = Y_{old}$ (i.e. Memory State for the D Latch)

$2)$ Make Enable(E)= $S = 1$, we get,

$Y_{new} = I_1 $ (i.e. output = input)

Hence, given circuit is equivalent to $D$ Latch.

Therefore, $\textbf{(B)}$

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Edit:

There is a misconception that "In latches, clock is not present". The following points are addressing this misconception.

(1) Latches and flip flops are the “bistable” elements because it is having two "stable" states Q=0 and Q=1 (stable means they are consistent with the original assumption on output Q).

(2) It should also be noted that a circuit can also have a third possible state with both outputs which is approximately halfway between 0 and 1 and this is called a metastable state.

(3) Since latches and flip flops are bistable stable element and so they are having $\log_2 2$=1 bit of information. Using the past values of output Q we can explain the future values of output Q and these bistable elements are also having the controlled inputs like S and R in S-R Latch or D in D-latch that control the states of output Q.

(4) In D-Latch, "D" stands for the "data" and it is a controlled input which control the next state of output Q.

(5) The clock input "CLK" decides when the input state should be changes. 

Please find the attachment from the book “digital design and computer architecture by harris & harris”:

here we have used the clock input "CLK" but it is still a D-Latch. 

(6) Now, comes to the D flip-flop, 

A D- flip flop can also be implemented by two D-latches as can be seen below and it is also from the same book as above:

 

(7) Flip flop works on the rising or falling edge (clock edge) of the clock so, the correct statements are "latch is level triggered" and "flip flop is edge triggered".

How we can implement the edge triggering, you can refer the above book for more details and all the above points are taken from the same book.

The triangle in the symbols denotes an edge-triggered clock input and here in the question, we are not implementing the "edge clock", "S" is a just simply a select input for the conventional multiplexer.

Comments

@John_Smith Thank you for asking the question too and sorry for the long comment.

Probably one can claim here that the options are not correct because some people take D Latch (Enable/Clock input is not present) and the gated D Latch differently. 

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@ankitgupta.1729 I see. Thank you for the tip, and no apologies necessary. The longer the explanation, the merrier is the experience :)

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S = clock

When s=0 (clock=0) mux gives the same previous output

When s = 1 (clock=1) mux acts as D circuit

So can we say it can be D flipflop also..!?

Answer 2

Many of us will think why this is not D flip flop as it is working like D flip flop also

No that is not the the case understand one basic difference that latches don't have clock but flip flops must have clock the clock is missing here so it is D flip flop only

Comments

Technically, it is not a correct statement that “latches don’t have a clock but flip flops must have a clock”.

Please check the below figure from a book `digital design and computer architecture by harris & harris`. Here D-Latch is also having a clock.

   

 

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Then can you clearify why this is latch and not flip flop

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Flip flop works for the rising or falling edge of the clock and to say it is a flip-flop, you have to implement the functionality of the “clock edge”. A D flip-flop can be implemented by using two D latches and an inverter or a NOR gate. So, if you want to make a D flip-flop from the above circuit, you will required two copies of the above circuit and an inverter.

I have added more details in my answer, so if you want, you can check it.

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s will be acting as a clock a here .

Answer 3

The output equation of $2\times1$ multiplexer :$Y=\overline SI_0+SI_1$

now put $S=0\rightarrow Y=I_0$

similarly put $S=1\rightarrow Y=I_1$

it is clearly a D-latch circuit.

Option (B) is correct.

Comments

Is there no use of connection between $I_0$ and Y ?

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Yes , If Signal S is constant.

Answer 4

The circuit in the figure represents a D Latch and not a D Flip-Flop due to the following differences:

1. D Latch:

   • It is level-triggered.
   • The output Q follows the input D as long as the control signal S (or Enable) is active (high in this case).
   • When S=0, the latch retains its current state (feedback maintains Q).

2. D Flip-Flop:

   • It is edge-triggered (typically triggered on the rising or falling edge of a clock signal).
   • The output Q changes only at the clock edge, and not continuously when the clock is high or low.

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Why This Circuit is a D Latch:

• The circuit uses a multiplexer and the selection signal S determines whether the output Q is updated (transparent mode, S=1) or retained (hold mode, S=0).
• There is no clock signal in this circuit. Without a clock, edge-triggering is not possible, so this circuit cannot function as a flip-flop.
• Instead, the circuit operates based on the level of S, which aligns with the functionality of a D Latch.

Comments

@shubhamkumartrichy pls also give the diagram for D Flipflop

Answer 5