GATE CSE 2023 | Question: 11

Question

The output of a $2$-input multiplexer is connected back to one of its inputs as shown in the figure.

Match the functional equivalence of this circuit to one of the following options.

• A. $\text{D}$ Flip-flop
• B. $\text{D}$ Latch
• C. Half-adder
• D. Demultiplexer

Comments

B is the answer.

Answer 1

Here, input “0” is considered as $I_0$ and input “1” is considered as $I_1$ and output Q is considered as Y for the given MUX.

 

As we can see in the given figure that $I_0 = Y,$ $I_0$ is storing the previous state of output $Y.$

Now, the basic function of $D$ Latch is:

$1)$ When Enable(E) = $0,$ Output state has the same its previous state, we call it as Memory State or you can say informally as $Q_{n+1} = Q_n$

$2)$ When Enable(E) = $1,$ Output variable = Input variable

Now, here, make the setting as: 

Input: $I_1$ and Enable(E)= $S$

Now, As we have already seen that $I_0$ is storing the previous state of output. So, Say, previous state of output is $Y_{old}$ and Next state of output is $Y_{new}$

Now, According to the equation of $2 \times 1$ MUX i.e. $Y= \overline{S}I_0 + S I_1$

Since, $I_0 =Y_{old}$

Hence, we have

$Y_{new} = \overline{S}Y_{old} + S I_1$

Now,

$1)$ Make Enable(E)= $S = 0$, we get,

$Y_{new} = Y_{old}$ (i.e. Memory State for the D Latch)

$2)$ Make Enable(E)= $S = 1$, we get,

$Y_{new} = I_1 $ (i.e. output = input)

Hence, given circuit is equivalent to $D$ Latch.

Therefore, $\textbf{(B)}$

Answer 2

The output equation of $2\times1$ multiplexer :$Y=\overline SI_0+SI_1$

now put $S=0\rightarrow Y=I_0$

similarly put $S=1\rightarrow Y=I_1$

it is clearly a D-latch circuit.

Option (B) is correct.

Comments

Is there no use of connection between $I_0$ and Y ?